arch/arm/cpu/arm720t/tegra-common/cpu.c

   1 /*
   2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <common.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gp_padctrl.h>
  21 #include <asm/arch/pinmux.h>
  22 #include <asm/arch/tegra.h>
  23 #include <asm/arch-tegra/clk_rst.h>
  24 #include <asm/arch-tegra/pmc.h>
  25 #include <asm/arch-tegra/scu.h>
  26 #include "cpu.h"
  27
  28 enum tegra_family_t {
  29         TEGRA_FAMILY_T2x,
  30         TEGRA_FAMILY_T3x,
  31 };
  32
  33
  34 enum tegra_family_t get_family(void)
  35 {
  36         u32 reg, chip_id;
  37
  38         reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
  39
  40         chip_id = reg >> 8;
  41         chip_id &= 0xff;
  42         debug("  tegra_get_family: chip_id = %x\n", chip_id);
  43         if (chip_id == 0x30)
  44                 return TEGRA_FAMILY_T3x;
  45         else
  46                 return TEGRA_FAMILY_T2x;
  47 }
  48
  49 int get_num_cpus(void)
  50 {
  51         return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
  52 }
  53
  54 /*
  55  * Timing tables for each SOC for all four oscillator options.
  56  */
  57 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  58         /* T20: 1 GHz */
  59         {{ 1000, 13, 0, 12},    /* OSC 13M */
  60          { 625,  12, 0, 8},     /* OSC 19.2M */
  61          { 1000, 12, 0, 12},    /* OSC 12M */
  62          { 1000, 26, 0, 12},    /* OSC 26M */
  63         },
  64
  65         /* T25: 1.2 GHz */
  66         {{ 923, 10, 0, 12},
  67          { 750, 12, 0, 8},
  68          { 600,  6, 0, 12},
  69          { 600, 13, 0, 12},
  70         },
  71
  72         /* T30: 1.4 GHz */
  73         {{ 862, 8, 0, 8},
  74          { 583, 8, 0, 4},
  75          { 700, 6, 0, 8},
  76          { 700, 13, 0, 8},
  77         },
  78
  79         /* TEGRA_SOC2_SLOW: 312 MHz */
  80         {{ 312, 13, 0, 12},     /* OSC 13M */
  81          { 260, 16, 0, 8},      /* OSC 19.2M */
  82          { 312, 12, 0, 12},     /* OSC 12M */
  83          { 312, 26, 0, 12},     /* OSC 26M */
  84         },
  85 };
  86
  87 void adjust_pllp_out_freqs(void)
  88 {
  89         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  90         struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
  91         u32 reg;
  92
  93         /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
  94         reg = readl(&pll->pll_out[0]);  /* OUTA, contains OUT2 / OUT1 */
  95         reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
  96                 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
  97         writel(reg, &pll->pll_out[0]);
  98
  99         reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
 100         reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
 101                 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
 102         writel(reg, &pll->pll_out[1]);
 103 }
 104
 105 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 106                 u32 divp, u32 cpcon)
 107 {
 108         u32 reg;
 109
 110         /* If PLLX is already enabled, just return */
 111         if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
 112                 debug("pllx_set_rate: PLLX already enabled, returning\n");
 113                 return 0;
 114         }
 115
 116         debug(" pllx_set_rate entry\n");
 117
 118         /* Set BYPASS, m, n and p to PLLX_BASE */
 119         reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
 120         reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
 121         writel(reg, &pll->pll_base);
 122
 123         /* Set cpcon to PLLX_MISC */
 124         reg = (cpcon << PLL_CPCON_SHIFT);
 125
 126         /* Set dccon to PLLX_MISC if freq > 600MHz */
 127         if (divn > 600)
 128                 reg |= (1 << PLL_DCCON_SHIFT);
 129         writel(reg, &pll->pll_misc);
 130
 131         /* Enable PLLX */
 132         reg = readl(&pll->pll_base);
 133         reg |= PLL_ENABLE_MASK;
 134
 135         /* Disable BYPASS */
 136         reg &= ~PLL_BYPASS_MASK;
 137         writel(reg, &pll->pll_base);
 138
 139         /* Set lock_enable to PLLX_MISC */
 140         reg = readl(&pll->pll_misc);
 141         reg |= PLL_LOCK_ENABLE_MASK;
 142         writel(reg, &pll->pll_misc);
 143
 144         return 0;
 145 }
 146
 147 void init_pllx(void)
 148 {
 149         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 150         struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
 151         int chip_type;
 152         enum clock_osc_freq osc;
 153         struct clk_pll_table *sel;
 154
 155         debug("init_pllx entry\n");
 156
 157         /* get chip type */
 158         chip_type = tegra_get_chip_type();
 159         debug(" init_pllx: chip_type = %d\n", chip_type);
 160
 161         /* get osc freq */
 162         osc = clock_get_osc_freq();
 163         debug("  init_pllx: osc = %d\n", osc);
 164
 165         /* set pllx */
 166         sel = &tegra_pll_x_table[chip_type][osc];
 167         pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
 168
 169         /* adjust PLLP_out1-4 on T30 */
 170         if (chip_type == TEGRA_SOC_T30) {
 171                 debug("  init_pllx: adjusting PLLP out freqs\n");
 172                 adjust_pllp_out_freqs();
 173         }
 174 }
 175
 176 void enable_cpu_clock(int enable)
 177 {
 178         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 179         u32 clk;
 180
 181         /*
 182          * NOTE:
 183          * Regardless of whether the request is to enable or disable the CPU
 184          * clock, every processor in the CPU complex except the master (CPU 0)
 185          * will have it's clock stopped because the AVP only talks to the
 186          * master.
 187          */
 188
 189         if (enable) {
 190                 /* Initialize PLLX */
 191                 init_pllx();
 192
 193                 /* Wait until all clocks are stable */
 194                 udelay(PLL_STABILIZATION_DELAY);
 195
 196                 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
 197                 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
 198         }
 199
 200         /*
 201          * Read the register containing the individual CPU clock enables and
 202          * always stop the clocks to CPUs > 0.
 203          */
 204         clk = readl(&clkrst->crc_clk_cpu_cmplx);
 205         clk |= 1 << CPU1_CLK_STP_SHIFT;
 206 #if defined(CONFIG_TEGRA30)
 207         clk |= 1 << CPU2_CLK_STP_SHIFT;
 208         clk |= 1 << CPU3_CLK_STP_SHIFT;
 209 #endif
 210         /* Stop/Unstop the CPU clock */
 211         clk &= ~CPU0_CLK_STP_MASK;
 212         clk |= !enable << CPU0_CLK_STP_SHIFT;
 213         writel(clk, &clkrst->crc_clk_cpu_cmplx);
 214
 215         clock_enable(PERIPH_ID_CPU);
 216 }
 217
 218 static int is_cpu_powered(void)
 219 {
 220         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 221
 222         return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 223 }
 224
 225 static void remove_cpu_io_clamps(void)
 226 {
 227         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 228         u32 reg;
 229
 230         /* Remove the clamps on the CPU I/O signals */
 231         reg = readl(&pmc->pmc_remove_clamping);
 232         reg |= CPU_CLMP;
 233         writel(reg, &pmc->pmc_remove_clamping);
 234
 235         /* Give I/O signals time to stabilize */
 236         udelay(IO_STABILIZATION_DELAY);
 237 }
 238
 239 void powerup_cpu(void)
 240 {
 241         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 242         u32 reg;
 243         int timeout = IO_STABILIZATION_DELAY;
 244
 245         if (!is_cpu_powered()) {
 246                 /* Toggle the CPU power state (OFF -> ON) */
 247                 reg = readl(&pmc->pmc_pwrgate_toggle);
 248                 reg &= PARTID_CP;
 249                 reg |= START_CP;
 250                 writel(reg, &pmc->pmc_pwrgate_toggle);
 251
 252                 /* Wait for the power to come up */
 253                 while (!is_cpu_powered()) {
 254                         if (timeout-- == 0)
 255                                 printf("CPU failed to power up!\n");
 256                         else
 257                                 udelay(10);
 258                 }
 259
 260                 /*
 261                  * Remove the I/O clamps from CPU power partition.
 262                  * Recommended only on a Warm boot, if the CPU partition gets
 263                  * power gated. Shouldn't cause any harm when called after a
 264                  * cold boot according to HW, probably just redundant.
 265                  */
 266                 remove_cpu_io_clamps();
 267         }
 268 }
 269
 270 void reset_A9_cpu(int reset)
 271 {
 272         /*
 273         * NOTE:  Regardless of whether the request is to hold the CPU in reset
 274         *        or take it out of reset, every processor in the CPU complex
 275         *        except the master (CPU 0) will be held in reset because the
 276         *        AVP only talks to the master. The AVP does not know that there
 277         *        are multiple processors in the CPU complex.
 278         */
 279         int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
 280         int num_cpus = get_num_cpus();
 281         int cpu;
 282
 283         debug("reset_a9_cpu entry\n");
 284         /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
 285         for (cpu = 1; cpu < num_cpus; cpu++)
 286                 reset_cmplx_set_enable(cpu, mask, 1);
 287         reset_cmplx_set_enable(0, mask, reset);
 288
 289         /* Enable/Disable master CPU reset */
 290         reset_set_enable(PERIPH_ID_CPU, reset);
 291 }
 292
 293 void clock_enable_coresight(int enable)
 294 {
 295         u32 rst, src;
 296
 297         debug("clock_enable_coresight entry\n");
 298         clock_set_enable(PERIPH_ID_CORESIGHT, enable);
 299         reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
 300
 301         if (enable) {
 302                 /*
 303                  * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
 304                  *  1.5, giving an effective frequency of 144MHz.
 305                  * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
 306                  *  (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
 307                  *
 308                  * Clock divider request for 204MHz would setup CSITE clock as
 309                  * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 310                  */
 311                 if (tegra_get_chip_type() == TEGRA_SOC_T30)
 312                         src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
 313                 else
 314                         src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
 315                 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 316
 317                 /* Unlock the CPU CoreSight interfaces */
 318                 rst = CORESIGHT_UNLOCK;
 319                 writel(rst, CSITE_CPU_DBG0_LAR);
 320                 writel(rst, CSITE_CPU_DBG1_LAR);
 321 #if defined(CONFIG_TEGRA30)
 322                 writel(rst, CSITE_CPU_DBG2_LAR);
 323                 writel(rst, CSITE_CPU_DBG3_LAR);
 324 #endif
 325         }
 326 }
 327
 328 void halt_avp(void)
 329 {
 330         for (;;) {
 331                 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
 332                         | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
 333                         FLOW_CTLR_HALT_COP_EVENTS);
 334         }
 335 }