arch/arm/cpu/arm920t/at91/clock.c

   1 /*
   2  * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
   3  *
   4  * Copyright (C) 2011 Andreas Bießmann
   5  * Copyright (C) 2005 David Brownell
   6  * Copyright (C) 2005 Ivan Kokshaysky
   7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14 #include <common.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/at91_pmc.h>
  18 #include <asm/arch/clk.h>
  19
  20 #if !defined(CONFIG_AT91FAMILY)
  21 # error You need to define CONFIG_AT91FAMILY in your board config!
  22 #endif
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static unsigned long at91_css_to_rate(unsigned long css)
  27 {
  28         switch (css) {
  29         case AT91_PMC_MCKR_CSS_SLOW:
  30                 return CONFIG_SYS_AT91_SLOW_CLOCK;
  31         case AT91_PMC_MCKR_CSS_MAIN:
  32                 return gd->arch.main_clk_rate_hz;
  33         case AT91_PMC_MCKR_CSS_PLLA:
  34                 return gd->arch.plla_rate_hz;
  35         case AT91_PMC_MCKR_CSS_PLLB:
  36                 return gd->arch.pllb_rate_hz;
  37         }
  38
  39         return 0;
  40 }
  41
  42 #ifdef CONFIG_USB_ATMEL
  43 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  44 {
  45         unsigned i, div = 0, mul = 0, diff = 1 << 30;
  46         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  47
  48         /* PLL output max 240 MHz (or 180 MHz per errata) */
  49         if (out_freq > 240000000)
  50                 goto fail;
  51
  52         for (i = 1; i < 256; i++) {
  53                 int diff1;
  54                 unsigned input, mul1;
  55
  56                 /*
  57                  * PLL input between 1MHz and 32MHz per spec, but lower
  58                  * frequences seem necessary in some cases so allow 100K.
  59                  * Warning: some newer products need 2MHz min.
  60                  */
  61                 input = main_freq / i;
  62                 if (input < 100000)
  63                         continue;
  64                 if (input > 32000000)
  65                         continue;
  66
  67                 mul1 = out_freq / input;
  68                 if (mul1 > 2048)
  69                         continue;
  70                 if (mul1 < 2)
  71                         goto fail;
  72
  73                 diff1 = out_freq - input * mul1;
  74                 if (diff1 < 0)
  75                         diff1 = -diff1;
  76                 if (diff > diff1) {
  77                         diff = diff1;
  78                         div = i;
  79                         mul = mul1;
  80                         if (diff == 0)
  81                                 break;
  82                 }
  83         }
  84         if (i == 256 && diff > (out_freq >> 5))
  85                 goto fail;
  86         return ret | ((mul - 1) << 16) | div;
  87 fail:
  88         return 0;
  89 }
  90 #endif
  91
  92 static u32 at91_pll_rate(u32 freq, u32 reg)
  93 {
  94         unsigned mul, div;
  95
  96         div = reg & 0xff;
  97         mul = (reg >> 16) & 0x7ff;
  98         if (div && mul) {
  99                 freq /= div;
 100                 freq *= mul + 1;
 101         } else
 102                 freq = 0;
 103
 104         return freq;
 105 }
 106
 107 int at91_clock_init(unsigned long main_clock)
 108 {
 109         unsigned freq, mckr;
 110         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 111 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
 112         unsigned tmp;
 113         /*
 114          * When the bootloader initialized the main oscillator correctly,
 115          * there's no problem using the cycle counter.  But if it didn't,
 116          * or when using oscillator bypass mode, we must be told the speed
 117          * of the main clock.
 118          */
 119         if (!main_clock) {
 120                 do {
 121                         tmp = readl(&pmc->mcfr);
 122                 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 123                 tmp &= AT91_PMC_MCFR_MAINF_MASK;
 124                 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 125         }
 126 #endif
 127         gd->arch.main_clk_rate_hz = main_clock;
 128
 129         /* report if PLLA is more than mildly overclocked */
 130         gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 131
 132 #ifdef CONFIG_USB_ATMEL
 133         /*
 134          * USB clock init:  choose 48 MHz PLLB value,
 135          * disable 48MHz clock during usb peripheral suspend.
 136          *
 137          * REVISIT:  assumes MCK doesn't derive from PLLB!
 138          */
 139         gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 140                              AT91_PMC_PLLBR_USBDIV_2;
 141         gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
 142                                               gd->arch.at91_pllb_usb_init);
 143 #endif
 144
 145         /*
 146          * MCK and CPU derive from one of those primary clocks.
 147          * For now, assume this parentage won't change.
 148          */
 149         mckr = readl(&pmc->mckr);
 150         gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
 151         freq = gd->arch.mck_rate_hz;
 152
 153         freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
 154         /* mdiv */
 155         gd->arch.mck_rate_hz = freq /
 156                         (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 157         gd->arch.cpu_clk_rate_hz = freq;
 158
 159         return 0;
 160 }