arch/arm/cpu/arm920t/at91/lowlevel_init.S

   1 /*
   2  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   3  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   4  *
   5  * Modified for the at91rm9200dk board by
   6  * (C) Copyright 2004
   7  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13
  14 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  15
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/at91_mc.h>
  18 #include <asm/arch/at91_pmc.h>
  19 #include <asm/arch/at91_pio.h>
  20
  21 #define ARM920T_CONTROL 0xC0000000      /* @ set bit 31 (iA) and 30 (nF) */
  22
  23 _MTEXT_BASE:
  24 #undef START_FROM_MEM
  25 #ifdef START_FROM_MEM
  26         .word   CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
  27 #else
  28         .word   CONFIG_SYS_TEXT_BASE
  29 #endif
  30
  31 .globl lowlevel_init
  32 lowlevel_init:
  33         ldr     r1, =AT91_ASM_PMC_MOR
  34         /* Main oscillator Enable register */
  35 #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
  36         ldr     r0, =0x0000FF01         /* Enable main oscillator */
  37 #else
  38         ldr     r0, =0x0000FF00         /* Disable main oscillator */
  39 #endif
  40         str     r0, [r1] /*AT91C_CKGR_MOR] */
  41         /* Add loop to compensate Main Oscillator startup time */
  42         ldr     r0, =0x00000010
  43 LoopOsc:
  44         subs    r0, r0, #1
  45         bhi     LoopOsc
  46
  47         /* memory control configuration */
  48         /* this isn't very elegant, but  what the heck */
  49         ldr     r0, =SMRDATA
  50         ldr     r1, _MTEXT_BASE
  51         sub     r0, r0, r1
  52         ldr     r2, =SMRDATAE
  53         sub     r2, r2, r1
  54 pllloop:
  55         /* the address */
  56         ldr     r1, [r0], #4
  57         /* the value */
  58         ldr     r3, [r0], #4
  59         str     r3, [r1]
  60         cmp     r2, r0
  61         bne     pllloop
  62         /* delay - this is all done by guess */
  63         ldr     r0, =0x00010000
  64         /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
  65 lock:
  66         subs    r0, r0, #1
  67         bhi     lock
  68         ldr     r0, =SMRDATA1
  69         ldr     r1, _MTEXT_BASE
  70         sub     r0, r0, r1
  71         ldr     r2, =SMRDATA1E
  72         sub     r2, r2, r1
  73 sdinit:
  74         /* the address */
  75         ldr     r1, [r0], #4
  76         /* the value */
  77         ldr     r3, [r0], #4
  78         str     r3, [r1]
  79         cmp     r2, r0
  80         bne     sdinit
  81
  82         /* switch from FastBus to Asynchronous clock mode */
  83         mrc     p15, 0, r0, c1, c0, 0
  84         orr     r0, r0, #ARM920T_CONTROL
  85         mcr     p15, 0, r0, c1, c0, 0
  86
  87         /* everything is fine now */
  88         mov     pc, lr
  89
  90         .ltorg
  91
  92 SMRDATA:
  93         .word AT91_ASM_MC_EBI_CFG
  94         .word CONFIG_SYS_EBI_CFGR_VAL
  95         .word AT91_ASM_MC_SMC_CSR0
  96         .word CONFIG_SYS_SMC_CSR0_VAL
  97         .word AT91_ASM_PMC_PLLAR
  98         .word CONFIG_SYS_PLLAR_VAL
  99         .word AT91_ASM_PMC_PLLBR
 100         .word CONFIG_SYS_PLLBR_VAL
 101         .word AT91_ASM_PMC_MCKR
 102         .word CONFIG_SYS_MCKR_VAL
 103 SMRDATAE:
 104         /* here there's a delay */
 105 SMRDATA1:
 106         .word AT91_ASM_PIOC_ASR
 107         .word CONFIG_SYS_PIOC_ASR_VAL
 108         .word AT91_ASM_PIOC_BSR
 109         .word CONFIG_SYS_PIOC_BSR_VAL
 110         .word AT91_ASM_PIOC_PDR
 111         .word CONFIG_SYS_PIOC_PDR_VAL
 112         .word AT91_ASM_MC_EBI_CSA
 113         .word CONFIG_SYS_EBI_CSA_VAL
 114         .word AT91_ASM_MC_SDRAMC_CR
 115         .word CONFIG_SYS_SDRC_CR_VAL
 116         .word AT91_ASM_MC_SDRAMC_MR
 117         .word CONFIG_SYS_SDRC_MR_VAL
 118         .word CONFIG_SYS_SDRAM
 119         .word CONFIG_SYS_SDRAM_VAL
 120         .word AT91_ASM_MC_SDRAMC_MR
 121         .word CONFIG_SYS_SDRC_MR_VAL1
 122         .word CONFIG_SYS_SDRAM
 123         .word CONFIG_SYS_SDRAM_VAL
 124         .word CONFIG_SYS_SDRAM
 125         .word CONFIG_SYS_SDRAM_VAL
 126         .word CONFIG_SYS_SDRAM
 127         .word CONFIG_SYS_SDRAM_VAL
 128         .word CONFIG_SYS_SDRAM
 129         .word CONFIG_SYS_SDRAM_VAL
 130         .word CONFIG_SYS_SDRAM
 131         .word CONFIG_SYS_SDRAM_VAL
 132         .word CONFIG_SYS_SDRAM
 133         .word CONFIG_SYS_SDRAM_VAL
 134         .word CONFIG_SYS_SDRAM
 135         .word CONFIG_SYS_SDRAM_VAL
 136         .word CONFIG_SYS_SDRAM
 137         .word CONFIG_SYS_SDRAM_VAL
 138         .word AT91_ASM_MC_SDRAMC_MR
 139         .word CONFIG_SYS_SDRC_MR_VAL2
 140         .word CONFIG_SYS_SDRAM1
 141         .word CONFIG_SYS_SDRAM_VAL
 142         .word AT91_ASM_MC_SDRAMC_TR
 143         .word CONFIG_SYS_SDRC_TR_VAL
 144         .word CONFIG_SYS_SDRAM
 145         .word CONFIG_SYS_SDRAM_VAL
 146         .word AT91_ASM_MC_SDRAMC_MR
 147         .word CONFIG_SYS_SDRC_MR_VAL3
 148         .word CONFIG_SYS_SDRAM
 149         .word CONFIG_SYS_SDRAM_VAL
 150 SMRDATA1E:
 151         /* SMRDATA1 is 176 bytes long */
 152 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */