arch/arm/cpu/arm920t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <asm-offsets.h>
  28 #include <common.h>
  29 #include <config.h>
  30
  31 /*
  32  *************************************************************************
  33  *
  34  * Jump vector table as in table 3.1 in [1]
  35  *
  36  *************************************************************************
  37  */
  38
  39
  40 .globl _start
  41 _start: b       start_code
  42         ldr     pc, _undefined_instruction
  43         ldr     pc, _software_interrupt
  44         ldr     pc, _prefetch_abort
  45         ldr     pc, _data_abort
  46         ldr     pc, _not_used
  47         ldr     pc, _irq
  48         ldr     pc, _fiq
  49
  50 _undefined_instruction: .word undefined_instruction
  51 _software_interrupt:    .word software_interrupt
  52 _prefetch_abort:        .word prefetch_abort
  53 _data_abort:            .word data_abort
  54 _not_used:              .word not_used
  55 _irq:                   .word irq
  56 _fiq:                   .word fiq
  57
  58         .balignl 16,0xdeadbeef
  59
  60
  61 /*
  62  *************************************************************************
  63  *
  64  * Startup Code (called from the ARM reset exception vector)
  65  *
  66  * do important init only if we don't start from memory!
  67  * relocate armboot to ram
  68  * setup stack
  69  * jump to second stage
  70  *
  71  *************************************************************************
  72  */
  73
  74 .globl _TEXT_BASE
  75 _TEXT_BASE:
  76         .word   CONFIG_SYS_TEXT_BASE
  77
  78 /*
  79  * These are defined in the board-specific linker script.
  80  * Subtracting _start from them lets the linker put their
  81  * relative position in the executable instead of leaving
  82  * them null.
  83  */
  84 .globl _bss_start_ofs
  85 _bss_start_ofs:
  86         .word __bss_start - _start
  87
  88 .globl _bss_end_ofs
  89 _bss_end_ofs:
  90         .word _end - _start
  91
  92 #ifdef CONFIG_USE_IRQ
  93 /* IRQ stack memory (calculated at run-time) */
  94 .globl IRQ_STACK_START
  95 IRQ_STACK_START:
  96         .word   0x0badc0de
  97
  98 /* IRQ stack memory (calculated at run-time) */
  99 .globl FIQ_STACK_START
 100 FIQ_STACK_START:
 101         .word 0x0badc0de
 102 #endif
 103
 104 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 105 .globl IRQ_STACK_START_IN
 106 IRQ_STACK_START_IN:
 107         .word   0x0badc0de
 108
 109 /*
 110  * the actual start code
 111  */
 112
 113 start_code:
 114         /*
 115          * set the cpu to SVC32 mode
 116          */
 117         mrs     r0, cpsr
 118         bic     r0, r0, #0x1f
 119         orr     r0, r0, #0xd3
 120         msr     cpsr, r0
 121
 122         bl      coloured_LED_init
 123         bl      red_LED_on
 124
 125 #if     defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 126         /*
 127          * relocate exception table
 128          */
 129         ldr     r0, =_start
 130         ldr     r1, =0x0
 131         mov     r2, #16
 132 copyex:
 133         subs    r2, r2, #1
 134         ldr     r3, [r0], #4
 135         str     r3, [r1], #4
 136         bne     copyex
 137 #endif
 138
 139 #ifdef CONFIG_S3C24X0
 140         /* turn off the watchdog */
 141
 142 # if defined(CONFIG_S3C2400)
 143 #  define pWTCON        0x15300000
 144 #  define INTMSK        0x14400008      /* Interupt-Controller base addresses */
 145 #  define CLKDIVN       0x14800014      /* clock divisor register */
 146 #else
 147 #  define pWTCON        0x53000000
 148 #  define INTMSK        0x4A000008      /* Interupt-Controller base addresses */
 149 #  define INTSUBMSK     0x4A00001C
 150 #  define CLKDIVN       0x4C000014      /* clock divisor register */
 151 # endif
 152
 153         ldr     r0, =pWTCON
 154         mov     r1, #0x0
 155         str     r1, [r0]
 156
 157         /*
 158          * mask all IRQs by setting all bits in the INTMR - default
 159          */
 160         mov     r1, #0xffffffff
 161         ldr     r0, =INTMSK
 162         str     r1, [r0]
 163 # if defined(CONFIG_S3C2410)
 164         ldr     r1, =0x3ff
 165         ldr     r0, =INTSUBMSK
 166         str     r1, [r0]
 167 # endif
 168
 169         /* FCLK:HCLK:PCLK = 1:2:4 */
 170         /* default FCLK is 120 MHz ! */
 171         ldr     r0, =CLKDIVN
 172         mov     r1, #3
 173         str     r1, [r0]
 174 #endif  /* CONFIG_S3C24X0 */
 175
 176         /*
 177          * we do sys-critical inits only at reboot,
 178          * not when booting from ram!
 179          */
 180 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 181         bl      cpu_init_crit
 182 #endif
 183
 184 /* Set stackpointer in internal RAM to call board_init_f */
 185 call_board_init_f:
 186         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 187         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 188         ldr     r0,=0x00000000
 189         bl      board_init_f
 190
 191 /*------------------------------------------------------------------------------*/
 192
 193 /*
 194  * void relocate_code (addr_sp, gd, addr_moni)
 195  *
 196  * This "function" does not return, instead it continues in RAM
 197  * after relocating the monitor code.
 198  *
 199  */
 200         .globl  relocate_code
 201 relocate_code:
 202         mov     r4, r0  /* save addr_sp */
 203         mov     r5, r1  /* save addr of gd */
 204         mov     r6, r2  /* save addr of destination */
 205
 206         /* Set up the stack                                                 */
 207 stack_setup:
 208         mov     sp, r4
 209
 210         adr     r0, _start
 211         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 212         ldr     r2, _TEXT_BASE
 213         ldr     r3, _bss_start_ofs
 214         add     r2, r0, r3              /* r2 <- source end address         */
 215         cmp     r0, r6
 216         beq     clear_bss
 217
 218 copy_loop:
 219         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 220         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 221         cmp     r0, r2                  /* until source end address [r2]    */
 222         blo     copy_loop
 223
 224 #ifndef CONFIG_PRELOADER
 225         /*
 226          * fix .rel.dyn relocations
 227          */
 228         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 229         sub     r9, r6, r0              /* r9 <- relocation offset */
 230         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 231         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 232         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 233         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 234         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 235         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 236 fixloop:
 237         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 238         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 239         ldr     r1, [r2, #4]
 240         and     r8, r1, #0xff
 241         cmp     r8, #23                 /* relative fixup? */
 242         beq     fixrel
 243         cmp     r8, #2                  /* absolute fixup? */
 244         beq     fixabs
 245         /* ignore unknown type of fixup */
 246         b       fixnext
 247 fixabs:
 248         /* absolute fix: set location to (offset) symbol value */
 249         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 250         add     r1, r10, r1             /* r1 <- address of symbol in table */
 251         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 252         add     r1, r9                  /* r1 <- relocated sym addr */
 253         b       fixnext
 254 fixrel:
 255         /* relative fix: increase location by offset */
 256         ldr     r1, [r0]
 257         add     r1, r1, r9
 258 fixnext:
 259         str     r1, [r0]
 260         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 261         cmp     r2, r3
 262         blo     fixloop
 263 #endif
 264
 265 clear_bss:
 266 #ifndef CONFIG_PRELOADER
 267         ldr     r0, _bss_start_ofs
 268         ldr     r1, _bss_end_ofs
 269         ldr     r3, _TEXT_BASE          /* Text base */
 270         mov     r4, r6                  /* reloc addr */
 271         add     r0, r0, r4
 272         add     r1, r1, r4
 273         mov     r2, #0x00000000         /* clear                            */
 274
 275 clbss_l:str     r2, [r0]                /* clear loop...                    */
 276         add     r0, r0, #4
 277         cmp     r0, r1
 278         bne     clbss_l
 279
 280         bl coloured_LED_init
 281         bl red_LED_on
 282 #endif
 283
 284 /*
 285  * We are done. Do not return, instead branch to second part of board
 286  * initialization, now running from RAM.
 287  */
 288 #ifdef CONFIG_NAND_SPL
 289         ldr     r0, _nand_boot_ofs
 290         mov     pc, r0
 291
 292 _nand_boot_ofs:
 293         .word nand_boot
 294 #else
 295         ldr     r0, _board_init_r_ofs
 296         adr     r1, _start
 297         add     lr, r0, r1
 298         add     lr, lr, r9
 299         /* setup parameters for board_init_r */
 300         mov     r0, r5          /* gd_t */
 301         mov     r1, r6          /* dest_addr */
 302         /* jump to it ... */
 303         mov     pc, lr
 304
 305 _board_init_r_ofs:
 306         .word board_init_r - _start
 307 #endif
 308
 309 _rel_dyn_start_ofs:
 310         .word __rel_dyn_start - _start
 311 _rel_dyn_end_ofs:
 312         .word __rel_dyn_end - _start
 313 _dynsym_start_ofs:
 314         .word __dynsym_start - _start
 315
 316 /*
 317  *************************************************************************
 318  *
 319  * CPU_init_critical registers
 320  *
 321  * setup important registers
 322  * setup memory timing
 323  *
 324  *************************************************************************
 325  */
 326
 327
 328 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 329 cpu_init_crit:
 330         /*
 331          * flush v4 I/D caches
 332          */
 333         mov     r0, #0
 334         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 335         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 336
 337         /*
 338          * disable MMU stuff and caches
 339          */
 340         mrc     p15, 0, r0, c1, c0, 0
 341         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 342         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 343         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 344         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 345         mcr     p15, 0, r0, c1, c0, 0
 346
 347         /*
 348          * before relocating, we have to setup RAM timing
 349          * because memory timing is board-dependend, you will
 350          * find a lowlevel_init.S in your board directory.
 351          */
 352         mov     ip, lr
 353
 354         bl      lowlevel_init
 355
 356         mov     lr, ip
 357         mov     pc, lr
 358 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 359
 360 /*
 361  *************************************************************************
 362  *
 363  * Interrupt handling
 364  *
 365  *************************************************************************
 366  */
 367
 368 @
 369 @ IRQ stack frame.
 370 @
 371 #define S_FRAME_SIZE    72
 372
 373 #define S_OLD_R0        68
 374 #define S_PSR           64
 375 #define S_PC            60
 376 #define S_LR            56
 377 #define S_SP            52
 378
 379 #define S_IP            48
 380 #define S_FP            44
 381 #define S_R10           40
 382 #define S_R9            36
 383 #define S_R8            32
 384 #define S_R7            28
 385 #define S_R6            24
 386 #define S_R5            20
 387 #define S_R4            16
 388 #define S_R3            12
 389 #define S_R2            8
 390 #define S_R1            4
 391 #define S_R0            0
 392
 393 #define MODE_SVC        0x13
 394 #define I_BIT           0x80
 395
 396 /*
 397  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 398  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 399  */
 400
 401         .macro  bad_save_user_regs
 402         sub     sp, sp, #S_FRAME_SIZE
 403         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 404         ldr     r2, IRQ_STACK_START_IN
 405         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 406         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 407
 408         add     r5, sp, #S_SP
 409         mov     r1, lr
 410         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 411         mov     r0, sp
 412         .endm
 413
 414         .macro  irq_save_user_regs
 415         sub     sp, sp, #S_FRAME_SIZE
 416         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 417         add     r7, sp, #S_PC
 418         stmdb   r7, {sp, lr}^                   @ Calling SP, LR
 419         str     lr, [r7, #0]                    @ Save calling PC
 420         mrs     r6, spsr
 421         str     r6, [r7, #4]                    @ Save CPSR
 422         str     r0, [r7, #8]                    @ Save OLD_R0
 423         mov     r0, sp
 424         .endm
 425
 426         .macro  irq_restore_user_regs
 427         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 428         mov     r0, r0
 429         ldr     lr, [sp, #S_PC]                 @ Get PC
 430         add     sp, sp, #S_FRAME_SIZE
 431         /* return & move spsr_svc into cpsr */
 432         subs    pc, lr, #4
 433         .endm
 434
 435         .macro get_bad_stack
 436         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 437
 438         str     lr, [r13]                       @ save caller lr / spsr
 439         mrs     lr, spsr
 440         str     lr, [r13, #4]
 441
 442         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 443         @ msr   spsr_c, r13
 444         msr     spsr, r13
 445         mov     lr, pc
 446         movs    pc, lr
 447         .endm
 448
 449         .macro get_irq_stack                    @ setup IRQ stack
 450         ldr     sp, IRQ_STACK_START
 451         .endm
 452
 453         .macro get_fiq_stack                    @ setup FIQ stack
 454         ldr     sp, FIQ_STACK_START
 455         .endm
 456
 457 /*
 458  * exception handlers
 459  */
 460         .align  5
 461 undefined_instruction:
 462         get_bad_stack
 463         bad_save_user_regs
 464         bl      do_undefined_instruction
 465
 466         .align  5
 467 software_interrupt:
 468         get_bad_stack
 469         bad_save_user_regs
 470         bl      do_software_interrupt
 471
 472         .align  5
 473 prefetch_abort:
 474         get_bad_stack
 475         bad_save_user_regs
 476         bl      do_prefetch_abort
 477
 478         .align  5
 479 data_abort:
 480         get_bad_stack
 481         bad_save_user_regs
 482         bl      do_data_abort
 483
 484         .align  5
 485 not_used:
 486         get_bad_stack
 487         bad_save_user_regs
 488         bl      do_not_used
 489
 490 #ifdef CONFIG_USE_IRQ
 491
 492         .align  5
 493 irq:
 494         get_irq_stack
 495         irq_save_user_regs
 496         bl      do_irq
 497         irq_restore_user_regs
 498
 499         .align  5
 500 fiq:
 501         get_fiq_stack
 502         /* someone ought to write a more effiction fiq_save_user_regs */
 503         irq_save_user_regs
 504         bl      do_fiq
 505         irq_restore_user_regs
 506
 507 #else
 508
 509         .align  5
 510 irq:
 511         get_bad_stack
 512         bad_save_user_regs
 513         bl      do_irq
 514
 515         .align  5
 516 fiq:
 517         get_bad_stack
 518         bad_save_user_regs
 519         bl      do_fiq
 520
 521 #endif