arch/arm/cpu/arm925t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM925 CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1510 from ARM920 code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij  <kshitij@ti.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #include <asm-offsets.h>
  34 #include <config.h>
  35 #include <version.h>
  36
  37 /*
  38  *************************************************************************
  39  *
  40  * Jump vector table as in table 3.1 in [1]
  41  *
  42  *************************************************************************
  43  */
  44
  45
  46 .globl _start
  47 _start: b       reset
  48         ldr     pc, _undefined_instruction
  49         ldr     pc, _software_interrupt
  50         ldr     pc, _prefetch_abort
  51         ldr     pc, _data_abort
  52         ldr     pc, _not_used
  53         ldr     pc, _irq
  54         ldr     pc, _fiq
  55
  56 _undefined_instruction: .word undefined_instruction
  57 _software_interrupt:    .word software_interrupt
  58 _prefetch_abort:        .word prefetch_abort
  59 _data_abort:            .word data_abort
  60 _not_used:              .word not_used
  61 _irq:                   .word irq
  62 _fiq:                   .word fiq
  63
  64         .balignl 16,0xdeadbeef
  65
  66
  67 /*
  68  *************************************************************************
  69  *
  70  * Startup Code (reset vector)
  71  *
  72  * do important init only if we don't start from memory!
  73  * setup Memory and board specific bits prior to relocation.
  74  * relocate armboot to ram
  75  * setup stack
  76  *
  77  *************************************************************************
  78  */
  79
  80 .globl _TEXT_BASE
  81 _TEXT_BASE:
  82 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  83         .word   CONFIG_SPL_TEXT_BASE
  84 #else
  85         .word   CONFIG_SYS_TEXT_BASE
  86 #endif
  87
  88 /*
  89  * These are defined in the board-specific linker script.
  90  * Subtracting _start from them lets the linker put their
  91  * relative position in the executable instead of leaving
  92  * them null.
  93  */
  94 .globl _bss_start_ofs
  95 _bss_start_ofs:
  96         .word __bss_start - _start
  97
  98 .globl _bss_end_ofs
  99 _bss_end_ofs:
 100         .word __bss_end - _start
 101
 102 .globl _end_ofs
 103 _end_ofs:
 104         .word _end - _start
 105
 106 #ifdef CONFIG_USE_IRQ
 107 /* IRQ stack memory (calculated at run-time) */
 108 .globl IRQ_STACK_START
 109 IRQ_STACK_START:
 110         .word   0x0badc0de
 111
 112 /* IRQ stack memory (calculated at run-time) */
 113 .globl FIQ_STACK_START
 114 FIQ_STACK_START:
 115         .word 0x0badc0de
 116 #endif
 117
 118 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 119 .globl IRQ_STACK_START_IN
 120 IRQ_STACK_START_IN:
 121         .word   0x0badc0de
 122
 123 /*
 124  * the actual reset code
 125  */
 126
 127 reset:
 128         /*
 129          * set the cpu to SVC32 mode
 130          */
 131         mrs     r0,cpsr
 132         bic     r0,r0,#0x1f
 133         orr     r0,r0,#0xd3
 134         msr     cpsr,r0
 135
 136         /*
 137          * Set up 925T mode
 138          */
 139         mov r1, #0x81               /* Set ARM925T configuration. */
 140         mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
 141
 142         /*
 143          * turn off the watchdog, unlock/diable sequence
 144          */
 145         mov  r1, #0xF5
 146         ldr  r0, =WDTIM_MODE
 147         strh r1, [r0]
 148         mov  r1, #0xA0
 149         strh r1, [r0]
 150
 151         /*
 152          * mask all IRQs by setting all bits in the INTMR - default
 153          */
 154         mov r1, #0xffffffff
 155         ldr r0, =REG_IHL1_MIR
 156         str r1, [r0]
 157         ldr r0, =REG_IHL2_MIR
 158         str r1, [r0]
 159
 160         /*
 161          * wait for dpll to lock
 162          */
 163         ldr  r0, =CK_DPLL1
 164         mov  r1, #0x10
 165         strh r1, [r0]
 166 poll1:
 167         ldrh r1, [r0]
 168         ands r1, r1, #0x01
 169         beq poll1
 170
 171         /*
 172          * we do sys-critical inits only at reboot,
 173          * not when booting from ram!
 174          */
 175 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 176         bl  cpu_init_crit
 177 #endif
 178
 179         bl      _main
 180
 181 /*------------------------------------------------------------------------------*/
 182
 183 /*
 184  * void relocate_code (addr_sp, gd, addr_moni)
 185  *
 186  * This "function" does not return, instead it continues in RAM
 187  * after relocating the monitor code.
 188  *
 189  */
 190         .globl  relocate_code
 191 relocate_code:
 192         mov     r4, r0  /* save addr_sp */
 193         mov     r5, r1  /* save addr of gd */
 194         mov     r6, r2  /* save addr of destination */
 195
 196         adr     r0, _start
 197         cmp     r0, r6
 198         moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
 199         beq     relocate_done           /* skip relocation */
 200         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 201         ldr     r3, _bss_start_ofs
 202         add     r2, r0, r3              /* r2 <- source end address         */
 203
 204 copy_loop:
 205         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 206         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 207         cmp     r0, r2                  /* until source end address [r2]    */
 208         blo     copy_loop
 209
 210 #ifndef CONFIG_SPL_BUILD
 211         /*
 212          * fix .rel.dyn relocations
 213          */
 214         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 215         sub     r9, r6, r0              /* r9 <- relocation offset */
 216         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 217         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 218         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 219         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 220         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 221         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 222 fixloop:
 223         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 224         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 225         ldr     r1, [r2, #4]
 226         and     r7, r1, #0xff
 227         cmp     r7, #23                 /* relative fixup? */
 228         beq     fixrel
 229         cmp     r7, #2                  /* absolute fixup? */
 230         beq     fixabs
 231         /* ignore unknown type of fixup */
 232         b       fixnext
 233 fixabs:
 234         /* absolute fix: set location to (offset) symbol value */
 235         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 236         add     r1, r10, r1             /* r1 <- address of symbol in table */
 237         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 238         add     r1, r1, r9              /* r1 <- relocated sym addr */
 239         b       fixnext
 240 fixrel:
 241         /* relative fix: increase location by offset */
 242         ldr     r1, [r0]
 243         add     r1, r1, r9
 244 fixnext:
 245         str     r1, [r0]
 246         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 247         cmp     r2, r3
 248         blo     fixloop
 249 #endif
 250
 251 relocate_done:
 252
 253         mov     pc, lr
 254
 255 _rel_dyn_start_ofs:
 256         .word __rel_dyn_start - _start
 257 _rel_dyn_end_ofs:
 258         .word __rel_dyn_end - _start
 259 _dynsym_start_ofs:
 260         .word __dynsym_start - _start
 261
 262         .globl  c_runtime_cpu_setup
 263 c_runtime_cpu_setup:
 264
 265         mov     pc, lr
 266
 267 /*
 268  *************************************************************************
 269  *
 270  * CPU_init_critical registers
 271  *
 272  * setup important registers
 273  * setup memory timing
 274  *
 275  *************************************************************************
 276  */
 277
 278
 279 cpu_init_crit:
 280         /*
 281          * flush v4 I/D caches
 282          */
 283         mov     r0, #0
 284         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 285         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 286
 287         /*
 288          * disable MMU stuff and caches
 289          */
 290         mrc     p15, 0, r0, c1, c0, 0
 291         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 292         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 293         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 294         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 295         mcr     p15, 0, r0, c1, c0, 0
 296
 297         /*
 298          * Go setup Memory and board specific bits prior to relocation.
 299          */
 300         mov     ip, lr          /* perserve link reg across call */
 301         bl      lowlevel_init   /* go setup pll,mux,memory */
 302         mov     lr, ip          /* restore link */
 303         mov     pc, lr          /* back to my caller */
 304 /*
 305  *************************************************************************
 306  *
 307  * Interrupt handling
 308  *
 309  *************************************************************************
 310  */
 311
 312 @
 313 @ IRQ stack frame.
 314 @
 315 #define S_FRAME_SIZE    72
 316
 317 #define S_OLD_R0        68
 318 #define S_PSR           64
 319 #define S_PC            60
 320 #define S_LR            56
 321 #define S_SP            52
 322
 323 #define S_IP            48
 324 #define S_FP            44
 325 #define S_R10           40
 326 #define S_R9            36
 327 #define S_R8            32
 328 #define S_R7            28
 329 #define S_R6            24
 330 #define S_R5            20
 331 #define S_R4            16
 332 #define S_R3            12
 333 #define S_R2            8
 334 #define S_R1            4
 335 #define S_R0            0
 336
 337 #define MODE_SVC 0x13
 338 #define I_BIT    0x80
 339
 340 /*
 341  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 342  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 343  */
 344
 345         .macro  bad_save_user_regs
 346         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 347         stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 348
 349         ldr     r2, IRQ_STACK_START_IN
 350         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 351         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 352
 353         add     r5, sp, #S_SP
 354         mov     r1, lr
 355         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 356         mov     r0, sp                          @ save current stack into r0 (param register)
 357         .endm
 358
 359         .macro  irq_save_user_regs
 360         sub     sp, sp, #S_FRAME_SIZE
 361         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 362         add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 363         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 364         str     lr, [r8, #0]                    @ Save calling PC
 365         mrs     r6, spsr
 366         str     r6, [r8, #4]                    @ Save CPSR
 367         str     r0, [r8, #8]                    @ Save OLD_R0
 368         mov     r0, sp
 369         .endm
 370
 371         .macro  irq_restore_user_regs
 372         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 373         mov     r0, r0
 374         ldr     lr, [sp, #S_PC]                 @ Get PC
 375         add     sp, sp, #S_FRAME_SIZE
 376         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 377         .endm
 378
 379         .macro get_bad_stack
 380         ldr     r13, IRQ_STACK_START_IN
 381
 382         str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 383         mrs     lr, spsr                        @ get the spsr
 384         str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 385
 386         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 387         @ msr   spsr_c, r13
 388         msr     spsr, r13                       @ switch modes, make sure moves will execute
 389         mov     lr, pc                          @ capture return pc
 390         movs    pc, lr                          @ jump to next instruction & switch modes.
 391         .endm
 392
 393         .macro get_irq_stack                    @ setup IRQ stack
 394         ldr     sp, IRQ_STACK_START
 395         .endm
 396
 397         .macro get_fiq_stack                    @ setup FIQ stack
 398         ldr     sp, FIQ_STACK_START
 399         .endm
 400
 401 /*
 402  * exception handlers
 403  */
 404         .align  5
 405 undefined_instruction:
 406         get_bad_stack
 407         bad_save_user_regs
 408         bl      do_undefined_instruction
 409
 410         .align  5
 411 software_interrupt:
 412         get_bad_stack
 413         bad_save_user_regs
 414         bl      do_software_interrupt
 415
 416         .align  5
 417 prefetch_abort:
 418         get_bad_stack
 419         bad_save_user_regs
 420         bl      do_prefetch_abort
 421
 422         .align  5
 423 data_abort:
 424         get_bad_stack
 425         bad_save_user_regs
 426         bl      do_data_abort
 427
 428         .align  5
 429 not_used:
 430         get_bad_stack
 431         bad_save_user_regs
 432         bl      do_not_used
 433
 434 #ifdef CONFIG_USE_IRQ
 435
 436         .align  5
 437 irq:
 438         get_irq_stack
 439         irq_save_user_regs
 440         bl      do_irq
 441         irq_restore_user_regs
 442
 443         .align  5
 444 fiq:
 445         get_fiq_stack
 446         /* someone ought to write a more effiction fiq_save_user_regs */
 447         irq_save_user_regs
 448         bl      do_fiq
 449         irq_restore_user_regs
 450
 451 #else
 452
 453         .align  5
 454 irq:
 455         get_bad_stack
 456         bad_save_user_regs
 457         bl      do_irq
 458
 459         .align  5
 460 fiq:
 461         get_bad_stack
 462         bad_save_user_regs
 463         bl      do_fiq
 464
 465 #endif
 466
 467         .align  5
 468 .globl reset_cpu
 469 reset_cpu:
 470         ldr     r1, rstctl1     /* get clkm1 reset ctl */
 471         mov     r3, #0x3        /* dsp_en + arm_rst = global reset */
 472         strh    r3, [r1]        /* force reset */
 473         mov     r0, r0
 474 _loop_forever:
 475         b       _loop_forever
 476 rstctl1:
 477         .word   0xfffece10