arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/arch/at91_common.h>
  31 #include <asm/arch/at91_pmc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34
  35 void at91_serial0_hw_init(void)
  36 {
  37         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  38
  39         at91_set_a_periph(AT91_PIO_PORTA, 22, 1);               /* TXD0 */
  40         at91_set_a_periph(AT91_PIO_PORTA, 23, 0);               /* RXD0 */
  41         writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
  42 }
  43
  44 void at91_serial1_hw_init(void)
  45 {
  46         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  47
  48         at91_set_a_periph(AT91_PIO_PORTD, 0, 1);                /* TXD1 */
  49         at91_set_a_periph(AT91_PIO_PORTD, 1, 0);                /* RXD1 */
  50         writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
  51 }
  52
  53 void at91_serial2_hw_init(void)
  54 {
  55         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  56
  57         at91_set_a_periph(AT91_PIO_PORTD, 2, 1);                /* TXD2 */
  58         at91_set_a_periph(AT91_PIO_PORTD, 3, 0);                /* RXD2 */
  59         writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
  60 }
  61
  62 void at91_serial3_hw_init(void)
  63 {
  64         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  65
  66         at91_set_a_periph(AT91_PIO_PORTC, 30, 0);               /* DRXD */
  67         at91_set_a_periph(AT91_PIO_PORTC, 31, 1);               /* DTXD */
  68         writel(1 << AT91_ID_SYS, &pmc->pcer);
  69 }
  70
  71 void at91_serial_hw_init(void)
  72 {
  73 #ifdef CONFIG_USART0
  74         at91_serial0_hw_init();
  75 #endif
  76
  77 #ifdef CONFIG_USART1
  78         at91_serial1_hw_init();
  79 #endif
  80
  81 #ifdef CONFIG_USART2
  82         at91_serial2_hw_init();
  83 #endif
  84
  85 #ifdef CONFIG_USART3    /* DBGU */
  86         at91_serial3_hw_init();
  87 #endif
  88 }
  89
  90 #ifdef CONFIG_HAS_DATAFLASH
  91 void at91_spi0_hw_init(unsigned long cs_mask)
  92 {
  93         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  94
  95         at91_set_b_periph(AT91_PIO_PORTA, 0, 0);        /* SPI0_MISO */
  96         at91_set_b_periph(AT91_PIO_PORTA, 1, 0);        /* SPI0_MOSI */
  97         at91_set_b_periph(AT91_PIO_PORTA, 2, 0);        /* SPI0_SPCK */
  98
  99         /* Enable clock */
 100         writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
 101
 102         if (cs_mask & (1 << 0)) {
 103                 at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
 104         }
 105         if (cs_mask & (1 << 1)) {
 106                 at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
 107         }
 108         if (cs_mask & (1 << 2)) {
 109                 at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
 110         }
 111         if (cs_mask & (1 << 3)) {
 112                 at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
 113         }
 114         if (cs_mask & (1 << 4)) {
 115                 at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
 116         }
 117         if (cs_mask & (1 << 5)) {
 118                 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
 119         }
 120         if (cs_mask & (1 << 6)) {
 121                 at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
 122         }
 123         if (cs_mask & (1 << 7)) {
 124                 at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
 125         }
 126 }
 127
 128 void at91_spi1_hw_init(unsigned long cs_mask)
 129 {
 130         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
 131
 132         at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* SPI1_MISO */
 133         at91_set_a_periph(AT91_PIO_PORTB, 13, 0);       /* SPI1_MOSI */
 134         at91_set_a_periph(AT91_PIO_PORTB, 14, 0);       /* SPI1_SPCK */
 135
 136         /* Enable clock */
 137         writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
 138
 139         if (cs_mask & (1 << 0)) {
 140                 at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
 141         }
 142         if (cs_mask & (1 << 1)) {
 143                 at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
 144         }
 145         if (cs_mask & (1 << 2)) {
 146                 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
 147         }
 148         if (cs_mask & (1 << 3)) {
 149                 at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
 150         }
 151         if (cs_mask & (1 << 4)) {
 152                 at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
 153         }
 154         if (cs_mask & (1 << 5)) {
 155                 at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
 156         }
 157         if (cs_mask & (1 << 6)) {
 158                 at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
 159         }
 160         if (cs_mask & (1 << 7)) {
 161                 at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
 162         }
 163
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_MACB
 168 void at91_macb_hw_init(void)
 169 {
 170         at91_set_a_periph(AT91_PIO_PORTB, 21, 0);       /* ETXCK_EREFCK */
 171         at91_set_a_periph(AT91_PIO_PORTB, 22, 0);       /* ERXDV */
 172         at91_set_a_periph(AT91_PIO_PORTB, 25, 0);       /* ERX0 */
 173         at91_set_a_periph(AT91_PIO_PORTB, 26, 0);       /* ERX1 */
 174         at91_set_a_periph(AT91_PIO_PORTB, 27, 0);       /* ERXER */
 175         at91_set_a_periph(AT91_PIO_PORTB, 28, 0);       /* ETXEN */
 176         at91_set_a_periph(AT91_PIO_PORTB, 23, 0);       /* ETX0 */
 177         at91_set_a_periph(AT91_PIO_PORTB, 24, 0);       /* ETX1 */
 178         at91_set_a_periph(AT91_PIO_PORTB, 30, 0);       /* EMDIO */
 179         at91_set_a_periph(AT91_PIO_PORTB, 29, 0);       /* EMDC */
 180
 181 #ifndef CONFIG_RMII
 182         at91_set_b_periph(AT91_PIO_PORTC, 25, 0);       /* ECRS */
 183         at91_set_b_periph(AT91_PIO_PORTC, 26, 0);       /* ECOL */
 184         at91_set_b_periph(AT91_PIO_PORTC, 22, 0);       /* ERX2 */
 185         at91_set_b_periph(AT91_PIO_PORTC, 23, 0);       /* ERX3 */
 186         at91_set_b_periph(AT91_PIO_PORTC, 27, 0);       /* ERXCK */
 187         at91_set_b_periph(AT91_PIO_PORTC, 20, 0);       /* ETX2 */
 188         at91_set_b_periph(AT91_PIO_PORTC, 21, 0);       /* ETX3 */
 189         at91_set_b_periph(AT91_PIO_PORTC, 24, 0);       /* ETXER */
 190 #endif
 191 }
 192 #endif
 193
 194 #ifdef CONFIG_AT91_CAN
 195 void at91_can_hw_init(void)
 196 {
 197         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
 198
 199         at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* CAN_TX */
 200         at91_set_a_periph(AT91_PIO_PORTA, 13, 1);       /* CAN_RX */
 201
 202         /* Enable clock */
 203         writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
 204 }
 205 #endif