arch/arm/cpu/arm926ejs/davinci/dm644x.c

   1 /*
   2  * SoC-specific code for tms320dm644x chips
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
   6  * Copyright (C) 2004 Texas Instruments.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <common.h>
  27 #include <asm/arch/hardware.h>
  28
  29
  30 #define PINMUX0_EMACEN (1 << 31)
  31 #define PINMUX0_AECS5  (1 << 11)
  32 #define PINMUX0_AECS4  (1 << 10)
  33
  34 #define PINMUX1_I2C    (1 <<  7)
  35 #define PINMUX1_UART1  (1 <<  1)
  36 #define PINMUX1_UART0  (1 <<  0)
  37
  38
  39 void davinci_enable_uart0(void)
  40 {
  41         lpsc_on(DAVINCI_LPSC_UART0);
  42
  43         /* Bringup UART0 out of reset */
  44         REG(UART0_PWREMU_MGMT) = 0x00006001;
  45
  46         /* Enable UART0 MUX lines */
  47         REG(PINMUX1) |= PINMUX1_UART0;
  48 }
  49
  50 #ifdef CONFIG_DRIVER_TI_EMAC
  51 void davinci_enable_emac(void)
  52 {
  53         lpsc_on(DAVINCI_LPSC_EMAC);
  54         lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
  55         lpsc_on(DAVINCI_LPSC_MDIO);
  56
  57         /* Enable GIO3.3V cells used for EMAC */
  58         REG(VDD3P3V_PWDN) = 0;
  59
  60         /* Enable EMAC. */
  61         REG(PINMUX0) |= PINMUX0_EMACEN;
  62 }
  63 #endif
  64
  65 #ifdef CONFIG_DRIVER_DAVINCI_I2C
  66 void davinci_enable_i2c(void)
  67 {
  68         lpsc_on(DAVINCI_LPSC_I2C);
  69
  70         /* Enable I2C pin Mux */
  71         REG(PINMUX1) |= PINMUX1_I2C;
  72 }
  73 #endif
  74
  75 void davinci_errata_workarounds(void)
  76 {
  77         /*
  78          * Workaround for TMS320DM6446 errata 1.3.22:
  79          *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
  80          *   Revision(s) Affected: 1.3 and earlier
  81          */
  82         REG(PSC_SILVER_BULLET) = 0;
  83
  84         /*
  85          * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
  86          * as suggested in TMS320DM6446 errata 2.1.2:
  87          *
  88          * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
  89          * low priority modules can occupy the bus and prevent high priority
  90          * modules like the VPSS from getting the required DDR2 throughput.
  91          * A hex value of 0x20 should provide a good ARM (cache enabled)
  92          * performance and still allow good utilization by the VPSS or other
  93          * modules.
  94          */
  95         REG(VBPR) = 0x20;
  96 }