arch/arm/cpu/arm926ejs/davinci/psc.c

   1 /*
   2  * Power and Sleep Controller (PSC) functions.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
   6  * Copyright (C) 2004 Texas Instruments.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <common.h>
  27 #include <asm/arch/hardware.h>
  28 #include <asm/io.h>
  29
  30 /*
  31  * The PSC manages three inputs to a "module" which may be a peripheral or
  32  * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
  33  * its power domain.  For our purposes, we only care whether clock and power
  34  * are active, and the module is out of reset.
  35  *
  36  * DaVinci chips may include two separate power domains: "Always On" and "DSP".
  37  * Chips without a DSP generally have only one domain.
  38  *
  39  * The "Always On" power domain is always on when the chip is on, and is
  40  * powered by the VDD pins (on DM644X). The majority of DaVinci modules
  41  * lie within the "Always On" power domain.
  42  *
  43  * A separate domain called the "DSP" domain houses the C64x+ and other video
  44  * hardware such as VICP. In some chips, the "DSP" domain is not always on.
  45  * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
  46  */
  47
  48 /* Works on Always On power domain only (no PD argument) */
  49 static void lpsc_transition(unsigned int id, unsigned int state)
  50 {
  51         dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  52 #ifdef CONFIG_SOC_DA8XX
  53         struct davinci_psc_regs *psc_regs;
  54 #endif
  55
  56 #ifndef CONFIG_SOC_DA8XX
  57         if (id >= DAVINCI_LPSC_GEM)
  58                 return;                 /* Don't work on DSP Power Domain */
  59
  60         mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
  61         mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
  62         ptstat = REG_P(PSC_PTSTAT);
  63         ptcmd = REG_P(PSC_PTCMD);
  64 #else
  65         if (id < DAVINCI_LPSC_PSC1_BASE) {
  66                 if (id >= PSC_PSC0_MODULE_ID_CNT)
  67                         return;
  68                 psc_regs = davinci_psc0_regs;
  69                 mdstat = &psc_regs->psc0.mdstat[id];
  70                 mdctl = &psc_regs->psc0.mdctl[id];
  71         } else {
  72                 id -= DAVINCI_LPSC_PSC1_BASE;
  73                 if (id >= PSC_PSC1_MODULE_ID_CNT)
  74                         return;
  75                 psc_regs = davinci_psc1_regs;
  76                 mdstat = &psc_regs->psc1.mdstat[id];
  77                 mdctl = &psc_regs->psc1.mdctl[id];
  78         }
  79         ptstat = &psc_regs->ptstat;
  80         ptcmd = &psc_regs->ptcmd;
  81 #endif
  82
  83         while (readl(ptstat) & 0x01)
  84                 continue;
  85
  86         if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
  87                 return; /* Already in that state */
  88
  89         writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
  90
  91         switch (id) {
  92 #ifdef CONFIG_SOC_DM644X
  93         /* Special treatment for some modules as for sprue14 p.7.4.2 */
  94         case DAVINCI_LPSC_VPSSSLV:
  95         case DAVINCI_LPSC_EMAC:
  96         case DAVINCI_LPSC_EMAC_WRAPPER:
  97         case DAVINCI_LPSC_MDIO:
  98         case DAVINCI_LPSC_USB:
  99         case DAVINCI_LPSC_ATA:
 100         case DAVINCI_LPSC_VLYNQ:
 101         case DAVINCI_LPSC_UHPI:
 102         case DAVINCI_LPSC_DDR_EMIF:
 103         case DAVINCI_LPSC_AEMIF:
 104         case DAVINCI_LPSC_MMC_SD:
 105         case DAVINCI_LPSC_MEMSTICK:
 106         case DAVINCI_LPSC_McBSP:
 107         case DAVINCI_LPSC_GPIO:
 108                 writel(readl(mdctl) | 0x200, mdctl);
 109                 break;
 110 #endif
 111         }
 112
 113         writel(0x01, ptcmd);
 114
 115         while (readl(ptstat) & 0x01)
 116                 continue;
 117         while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
 118                 continue;
 119 }
 120
 121 void lpsc_on(unsigned int id)
 122 {
 123         lpsc_transition(id, 0x03);
 124 }
 125
 126 void lpsc_syncreset(unsigned int id)
 127 {
 128         lpsc_transition(id, 0x01);
 129 }
 130
 131 void lpsc_disable(unsigned int id)
 132 {
 133         lpsc_transition(id, 0x0);
 134 }
 135
 136 /* Not all DaVinci chips have a DSP power domain. */
 137 #ifdef CONFIG_SOC_DM644X
 138
 139 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
 140 #if !defined(CONFIG_SYS_USE_DSPLINK)
 141 void dsp_on(void)
 142 {
 143         int i;
 144
 145         if (REG(PSC_PDSTAT1) & 0x1f)
 146                 return;                 /* Already on */
 147
 148         REG(PSC_GBLCTL) |= 0x01;
 149         REG(PSC_PDCTL1) |= 0x01;
 150         REG(PSC_PDCTL1) &= ~0x100;
 151         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
 152         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
 153         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
 154         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
 155         REG(PSC_PTCMD) = 0x02;
 156
 157         for (i = 0; i < 100; i++) {
 158                 if (REG(PSC_EPCPR) & 0x02)
 159                         break;
 160         }
 161
 162         REG(PSC_CHP_SHRTSW) = 0x01;
 163         REG(PSC_PDCTL1) |= 0x100;
 164         REG(PSC_EPCCR) = 0x02;
 165
 166         for (i = 0; i < 100; i++) {
 167                 if (!(REG(PSC_PTSTAT) & 0x02))
 168                         break;
 169         }
 170
 171         REG(PSC_GBLCTL) &= ~0x1f;
 172 }
 173 #endif /* CONFIG_SYS_USE_DSPLINK */
 174
 175 #endif /* have a DSP */