arch/arm/cpu/arm926ejs/mx28/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Groger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Zupke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
  14  *
  15  * Change to support call back into iMX28 bootrom
  16  * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  17  * on behalf of DENX Software Engineering GmbH
  18  *
  19  * See file CREDITS for list of people who contributed to this
  20  * project.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License as
  24  * published by the Free Software Foundation; either version 2 of
  25  * the License, or (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35  * MA 02111-1307 USA
  36  */
  37
  38 #include <asm-offsets.h>
  39 #include <config.h>
  40 #include <common.h>
  41 #include <version.h>
  42
  43 #if defined(CONFIG_OMAP1610)
  44 #include <./configs/omap1510.h>
  45 #elif defined(CONFIG_OMAP730)
  46 #include <./configs/omap730.h>
  47 #endif
  48
  49 /*
  50  *************************************************************************
  51  *
  52  * Jump vector table as in table 3.1 in [1]
  53  *
  54  *************************************************************************
  55  */
  56
  57
  58 .globl _start
  59 _start:
  60         b       reset
  61         b       undefined_instruction
  62         b       software_interrupt
  63         b       prefetch_abort
  64         b       data_abort
  65         b       not_used
  66         b       irq
  67         b       fiq
  68
  69 /*
  70  * Vector table, located at address 0x20.
  71  * This table allows the code running AFTER SPL, the U-Boot, to install it's
  72  * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
  73  * including it's interrupt vectoring table and the table at 0x0 is still the
  74  * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
  75  * is still used.
  76  */
  77 _vt_reset:
  78         .word   _reset
  79 _vt_undefined_instruction:
  80         .word   _hang
  81 _vt_software_interrupt:
  82         .word   _hang
  83 _vt_prefetch_abort:
  84         .word   _hang
  85 _vt_data_abort:
  86         .word   _hang
  87 _vt_not_used:
  88         .word   _reset
  89 _vt_irq:
  90         .word   _hang
  91 _vt_fiq:
  92         .word   _hang
  93
  94 reset:
  95         ldr     pc, _vt_reset
  96 undefined_instruction:
  97         ldr     pc, _vt_undefined_instruction
  98 software_interrupt:
  99         ldr     pc, _vt_software_interrupt
 100 prefetch_abort:
 101         ldr     pc, _vt_prefetch_abort
 102 data_abort:
 103         ldr     pc, _vt_data_abort
 104 not_used:
 105         ldr     pc, _vt_not_used
 106 irq:
 107         ldr     pc, _vt_irq
 108 fiq:
 109         ldr     pc, _vt_fiq
 110
 111         .balignl 16,0xdeadbeef
 112
 113 /*
 114  *************************************************************************
 115  *
 116  * Startup Code (reset vector)
 117  *
 118  * do important init only if we don't start from memory!
 119  * setup Memory and board specific bits prior to relocation.
 120  * relocate armboot to ram
 121  * setup stack
 122  *
 123  *************************************************************************
 124  */
 125
 126 .globl _TEXT_BASE
 127 _TEXT_BASE:
 128         .word   CONFIG_SYS_TEXT_BASE
 129
 130 /*
 131  * These are defined in the board-specific linker script.
 132  * Subtracting _start from them lets the linker put their
 133  * relative position in the executable instead of leaving
 134  * them null.
 135  */
 136 .globl _bss_start_ofs
 137 _bss_start_ofs:
 138         .word __bss_start - _start
 139
 140 .globl _bss_end_ofs
 141 _bss_end_ofs:
 142         .word __bss_end__ - _start
 143
 144 .globl _end_ofs
 145 _end_ofs:
 146         .word _end - _start
 147
 148 #ifdef CONFIG_USE_IRQ
 149 /* IRQ stack memory (calculated at run-time) */
 150 .globl IRQ_STACK_START
 151 IRQ_STACK_START:
 152         .word   0x0badc0de
 153
 154 /* IRQ stack memory (calculated at run-time) */
 155 .globl FIQ_STACK_START
 156 FIQ_STACK_START:
 157         .word 0x0badc0de
 158 #endif
 159
 160 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 161 .globl IRQ_STACK_START_IN
 162 IRQ_STACK_START_IN:
 163         .word   0x0badc0de
 164
 165 /*
 166  * the actual reset code
 167  */
 168
 169 _reset:
 170         /*
 171          * Store all registers on old stack pointer, this will allow us later to
 172          * return to the BootROM and let the BootROM load U-Boot into RAM.
 173          */
 174         push    {r0-r12,r14}
 175
 176         /*
 177          * set the cpu to SVC32 mode
 178          */
 179         mrs     r0,cpsr
 180         bic     r0,r0,#0x1f
 181         orr     r0,r0,#0xd3
 182         msr     cpsr,r0
 183
 184         /*
 185          * we do sys-critical inits only at reboot,
 186          * not when booting from ram!
 187          */
 188 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 189         bl      cpu_init_crit
 190 #endif
 191
 192         bl      board_init_ll
 193
 194         pop     {r0-r12,r14}
 195         bx      lr
 196
 197 /*
 198  *************************************************************************
 199  *
 200  * CPU_init_critical registers
 201  *
 202  * setup important registers
 203  * setup memory timing
 204  *
 205  *************************************************************************
 206  */
 207 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 208 cpu_init_crit:
 209         /*
 210          * flush v4 I/D caches
 211          */
 212         mov     r0, #0
 213         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 214         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 215
 216         /*
 217          * disable MMU stuff and caches
 218          */
 219         mrc     p15, 0, r0, c1, c0, 0
 220         bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
 221         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
 222         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 223         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 224         mcr     p15, 0, r0, c1, c0, 0
 225
 226         mov     pc, lr          /* back to my caller */
 227
 228         .align  5
 229 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 230
 231 _hang:
 232         ldr     sp, _TEXT_BASE                  /* switch to abort stack */
 233 1:
 234         bl      1b                              /* hang and never return */