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[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2 * Freescale i.MX28 Boot PMIC init
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14
15 #include "mxs_init.h"
16
17 /**
18 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
19 *
20 * This function switches the CPU core clock from PLL to 24MHz XTAL
21 * oscilator. This is necessary if the PLL is being reconfigured to
22 * prevent crash of the CPU core.
23 */
24 static void mxs_power_clock2xtal(void)
25 {
26 struct mxs_clkctrl_regs *clkctrl_regs =
27 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
28
29 /* Set XTAL as CPU reference clock */
30 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
31 &clkctrl_regs->hw_clkctrl_clkseq_set);
32 }
33
34 /**
35 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
36 *
37 * This function switches the CPU core clock from 24MHz XTAL oscilator
38 * to PLL. This can only be called once the PLL has re-locked and once
39 * the PLL is stable after reconfiguration.
40 */
41 static void mxs_power_clock2pll(void)
42 {
43 struct mxs_clkctrl_regs *clkctrl_regs =
44 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
45
46 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
47 CLKCTRL_PLL0CTRL0_POWER);
48 early_delay(100);
49 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
50 CLKCTRL_CLKSEQ_BYPASS_CPU);
51 }
52
53 /**
54 * mxs_power_set_auto_restart() - Set the auto-restart bit
55 *
56 * This function ungates the RTC block and sets the AUTO_RESTART
57 * bit to work around a design bug on MX28EVK Rev. A .
58 */
59
60 static void mxs_power_set_auto_restart(void)
61 {
62 struct mxs_rtc_regs *rtc_regs =
63 (struct mxs_rtc_regs *)MXS_RTC_BASE;
64
65 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
66 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
67 ;
68
69 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
70 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
71 ;
72
73 /* Do nothing if flag already set */
74 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
75 return;
76
77 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
78 ;
79
80 setbits_le32(&rtc_regs->hw_rtc_persistent0,
81 RTC_PERSISTENT0_AUTO_RESTART);
82 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
83 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
85 ;
86 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
87 ;
88 }
89
90 /**
91 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
92 *
93 * This function configures the VDDIO, VDDA and VDDD linear regulators output
94 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
95 * converter. This is the recommended setting for the case where we use both
96 * linear regulators and DC-DC converter to power the VDDIO rail.
97 */
98 static void mxs_power_set_linreg(void)
99 {
100 struct mxs_power_regs *power_regs =
101 (struct mxs_power_regs *)MXS_POWER_BASE;
102
103 /* Set linear regulator 25mV below switching converter */
104 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
105 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
106 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
107
108 clrsetbits_le32(&power_regs->hw_power_vddactrl,
109 POWER_VDDACTRL_LINREG_OFFSET_MASK,
110 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
111
112 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
113 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
114 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
115 }
116
117 /**
118 * mxs_get_batt_volt() - Measure battery input voltage
119 *
120 * This function retrieves the battery input voltage and returns it.
121 */
122 static int mxs_get_batt_volt(void)
123 {
124 struct mxs_power_regs *power_regs =
125 (struct mxs_power_regs *)MXS_POWER_BASE;
126 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
127 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
128 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
129 volt *= 8;
130 return volt;
131 }
132
133 /**
134 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
135 *
136 * This function checks if the battery input voltage is higher than 3.6V and
137 * therefore allows the system to successfully boot using this power source.
138 */
139 static int mxs_is_batt_ready(void)
140 {
141 return (mxs_get_batt_volt() >= 3600);
142 }
143
144 /**
145 * mxs_is_batt_good() - Test if battery is operational at all
146 *
147 * This function starts recharging the battery and tests if the input current
148 * provided by the 5V input recharging the battery is also sufficient to power
149 * the DC-DC converter.
150 */
151 static int mxs_is_batt_good(void)
152 {
153 struct mxs_power_regs *power_regs =
154 (struct mxs_power_regs *)MXS_POWER_BASE;
155 uint32_t volt = mxs_get_batt_volt();
156
157 if ((volt >= 2400) && (volt <= 4300))
158 return 1;
159
160 clrsetbits_le32(&power_regs->hw_power_5vctrl,
161 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
162 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
163 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
164 &power_regs->hw_power_5vctrl_clr);
165
166 clrsetbits_le32(&power_regs->hw_power_charge,
167 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
168 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
169
170 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
171 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
172 &power_regs->hw_power_5vctrl_clr);
173
174 early_delay(500000);
175
176 volt = mxs_get_batt_volt();
177
178 if (volt >= 3500)
179 return 0;
180
181 if (volt >= 2400)
182 return 1;
183
184 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
185 &power_regs->hw_power_charge_clr);
186 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
187
188 return 0;
189 }
190
191 /**
192 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
193 *
194 * This function enables the 5V detection comparator and sets the 5V valid
195 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
196 * under high load, the voltage drop on the 5V input won't be so critical
197 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
198 * converter and thus making the system crash.
199 */
200 static void mxs_power_setup_5v_detect(void)
201 {
202 struct mxs_power_regs *power_regs =
203 (struct mxs_power_regs *)MXS_POWER_BASE;
204
205 /* Start 5V detection */
206 clrsetbits_le32(&power_regs->hw_power_5vctrl,
207 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
208 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
209 POWER_5VCTRL_PWRUP_VBUS_CMPS);
210 }
211
212 /**
213 * mxs_src_power_init() - Preconfigure the power block
214 *
215 * This function configures reasonable values for the DC-DC control loop
216 * and battery monitor.
217 */
218 static void mxs_src_power_init(void)
219 {
220 struct mxs_power_regs *power_regs =
221 (struct mxs_power_regs *)MXS_POWER_BASE;
222
223 /* Improve efficieny and reduce transient ripple */
224 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
225 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
226
227 clrsetbits_le32(&power_regs->hw_power_dclimits,
228 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
229 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
230
231 setbits_le32(&power_regs->hw_power_battmonitor,
232 POWER_BATTMONITOR_EN_BATADJ);
233
234 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
235 clrsetbits_le32(&power_regs->hw_power_loopctrl,
236 POWER_LOOPCTRL_EN_RCSCALE_MASK,
237 POWER_LOOPCTRL_RCSCALE_THRESH |
238 POWER_LOOPCTRL_EN_RCSCALE_8X);
239
240 clrsetbits_le32(&power_regs->hw_power_minpwr,
241 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
242
243 /* 5V to battery handoff ... FIXME */
244 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
245 early_delay(30);
246 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
247 }
248
249 /**
250 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
251 *
252 * This function configures the necessary parameters for the 4P2 linear
253 * regulator to supply the DC-DC converter from 5V input.
254 */
255 static void mxs_power_init_4p2_params(void)
256 {
257 struct mxs_power_regs *power_regs =
258 (struct mxs_power_regs *)MXS_POWER_BASE;
259
260 /* Setup 4P2 parameters */
261 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
262 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
263 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
264
265 clrsetbits_le32(&power_regs->hw_power_5vctrl,
266 POWER_5VCTRL_HEADROOM_ADJ_MASK,
267 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
268
269 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
270 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
271 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
272 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
273
274 clrsetbits_le32(&power_regs->hw_power_5vctrl,
275 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
276 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
277 }
278
279 /**
280 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
281 * @xfer: Select if the input shall be enabled or disabled
282 *
283 * This function enables or disables the 4P2 input into the DC-DC converter.
284 */
285 static void mxs_enable_4p2_dcdc_input(int xfer)
286 {
287 struct mxs_power_regs *power_regs =
288 (struct mxs_power_regs *)MXS_POWER_BASE;
289 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
290 uint32_t prev_5v_brnout, prev_5v_droop;
291
292 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
293 POWER_5VCTRL_PWDN_5VBRNOUT;
294 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
295 POWER_CTRL_ENIRQ_VDD5V_DROOP;
296
297 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
298 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
299 &power_regs->hw_power_reset);
300
301 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
302
303 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
304 POWER_5VCTRL_ENABLE_DCDC)) {
305 return;
306 }
307
308 /*
309 * Recording orignal values that will be modified temporarlily
310 * to handle a chip bug. See chip errata for CQ ENGR00115837
311 */
312 tmp = readl(&power_regs->hw_power_5vctrl);
313 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
314 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
315
316 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
317
318 /*
319 * Disable mechanisms that get erroneously tripped by when setting
320 * the DCDC4P2 EN_DCDC
321 */
322 clrbits_le32(&power_regs->hw_power_5vctrl,
323 POWER_5VCTRL_VBUSVALID_5VDETECT |
324 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
325
326 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
327
328 if (xfer) {
329 setbits_le32(&power_regs->hw_power_5vctrl,
330 POWER_5VCTRL_DCDC_XFER);
331 early_delay(20);
332 clrbits_le32(&power_regs->hw_power_5vctrl,
333 POWER_5VCTRL_DCDC_XFER);
334
335 setbits_le32(&power_regs->hw_power_5vctrl,
336 POWER_5VCTRL_ENABLE_DCDC);
337 } else {
338 setbits_le32(&power_regs->hw_power_dcdc4p2,
339 POWER_DCDC4P2_ENABLE_DCDC);
340 }
341
342 early_delay(25);
343
344 clrsetbits_le32(&power_regs->hw_power_5vctrl,
345 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
346
347 if (vbus_5vdetect)
348 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
349
350 if (!pwd_bo)
351 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
352
353 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
354 writel(POWER_CTRL_VBUS_VALID_IRQ,
355 &power_regs->hw_power_ctrl_clr);
356
357 if (prev_5v_brnout) {
358 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
359 &power_regs->hw_power_5vctrl_set);
360 writel(POWER_RESET_UNLOCK_KEY,
361 &power_regs->hw_power_reset);
362 } else {
363 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
364 &power_regs->hw_power_5vctrl_clr);
365 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
366 &power_regs->hw_power_reset);
367 }
368
369 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
370 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
371 &power_regs->hw_power_ctrl_clr);
372
373 if (prev_5v_droop)
374 clrbits_le32(&power_regs->hw_power_ctrl,
375 POWER_CTRL_ENIRQ_VDD5V_DROOP);
376 else
377 setbits_le32(&power_regs->hw_power_ctrl,
378 POWER_CTRL_ENIRQ_VDD5V_DROOP);
379 }
380
381 /**
382 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
383 *
384 * This function enables the 4P2 regulator and switches the DC-DC converter
385 * to use the 4P2 input.
386 */
387 static void mxs_power_init_4p2_regulator(void)
388 {
389 struct mxs_power_regs *power_regs =
390 (struct mxs_power_regs *)MXS_POWER_BASE;
391 uint32_t tmp, tmp2;
392
393 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
394
395 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
396
397 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
398 &power_regs->hw_power_5vctrl_clr);
399 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
400
401 /* Power up the 4p2 rail and logic/control */
402 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
403 &power_regs->hw_power_5vctrl_clr);
404
405 /*
406 * Start charging up the 4p2 capacitor. We ramp of this charge
407 * gradually to avoid large inrush current from the 5V cable which can
408 * cause transients/problems
409 */
410 mxs_enable_4p2_dcdc_input(0);
411
412 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
413 /*
414 * If we arrived here, we were unable to recover from mx23 chip
415 * errata 5837. 4P2 is disabled and sufficient battery power is
416 * not present. Exiting to not enable DCDC power during 5V
417 * connected state.
418 */
419 clrbits_le32(&power_regs->hw_power_dcdc4p2,
420 POWER_DCDC4P2_ENABLE_DCDC);
421 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
422 &power_regs->hw_power_5vctrl_set);
423 hang();
424 }
425
426 /*
427 * Here we set the 4p2 brownout level to something very close to 4.2V.
428 * We then check the brownout status. If the brownout status is false,
429 * the voltage is already close to the target voltage of 4.2V so we
430 * can go ahead and set the 4P2 current limit to our max target limit.
431 * If the brownout status is true, we need to ramp us the current limit
432 * so that we don't cause large inrush current issues. We step up the
433 * current limit until the brownout status is false or until we've
434 * reached our maximum defined 4p2 current limit.
435 */
436 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
437 POWER_DCDC4P2_BO_MASK,
438 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
439
440 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
441 setbits_le32(&power_regs->hw_power_5vctrl,
442 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
443 } else {
444 tmp = (readl(&power_regs->hw_power_5vctrl) &
445 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
446 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
447 while (tmp < 0x3f) {
448 if (!(readl(&power_regs->hw_power_sts) &
449 POWER_STS_DCDC_4P2_BO)) {
450 tmp = readl(&power_regs->hw_power_5vctrl);
451 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
452 early_delay(100);
453 writel(tmp, &power_regs->hw_power_5vctrl);
454 break;
455 } else {
456 tmp++;
457 tmp2 = readl(&power_regs->hw_power_5vctrl);
458 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
459 tmp2 |= tmp <<
460 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
461 writel(tmp2, &power_regs->hw_power_5vctrl);
462 early_delay(100);
463 }
464 }
465 }
466
467 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
468 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
469 }
470
471 /**
472 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
473 *
474 * This function configures the DC-DC converter to be supplied from the 4P2
475 * linear regulator.
476 */
477 static void mxs_power_init_dcdc_4p2_source(void)
478 {
479 struct mxs_power_regs *power_regs =
480 (struct mxs_power_regs *)MXS_POWER_BASE;
481
482 if (!(readl(&power_regs->hw_power_dcdc4p2) &
483 POWER_DCDC4P2_ENABLE_DCDC)) {
484 hang();
485 }
486
487 mxs_enable_4p2_dcdc_input(1);
488
489 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
490 clrbits_le32(&power_regs->hw_power_dcdc4p2,
491 POWER_DCDC4P2_ENABLE_DCDC);
492 writel(POWER_5VCTRL_ENABLE_DCDC,
493 &power_regs->hw_power_5vctrl_clr);
494 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
495 &power_regs->hw_power_5vctrl_set);
496 }
497 }
498
499 /**
500 * mxs_power_enable_4p2() - Power up the 4P2 regulator
501 *
502 * This function drives the process of powering up the 4P2 linear regulator
503 * and switching the DC-DC converter input over to the 4P2 linear regulator.
504 */
505 static void mxs_power_enable_4p2(void)
506 {
507 struct mxs_power_regs *power_regs =
508 (struct mxs_power_regs *)MXS_POWER_BASE;
509 uint32_t vdddctrl, vddactrl, vddioctrl;
510 uint32_t tmp;
511
512 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
513 vddactrl = readl(&power_regs->hw_power_vddactrl);
514 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
515
516 setbits_le32(&power_regs->hw_power_vdddctrl,
517 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
518 POWER_VDDDCTRL_PWDN_BRNOUT);
519
520 setbits_le32(&power_regs->hw_power_vddactrl,
521 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
522 POWER_VDDACTRL_PWDN_BRNOUT);
523
524 setbits_le32(&power_regs->hw_power_vddioctrl,
525 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
526
527 mxs_power_init_4p2_params();
528 mxs_power_init_4p2_regulator();
529
530 /* Shutdown battery (none present) */
531 if (!mxs_is_batt_ready()) {
532 clrbits_le32(&power_regs->hw_power_dcdc4p2,
533 POWER_DCDC4P2_BO_MASK);
534 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
535 &power_regs->hw_power_ctrl_clr);
536 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
537 &power_regs->hw_power_ctrl_clr);
538 }
539
540 mxs_power_init_dcdc_4p2_source();
541
542 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
543 early_delay(20);
544 writel(vddactrl, &power_regs->hw_power_vddactrl);
545 early_delay(20);
546 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
547
548 /*
549 * Check if FET is enabled on either powerout and if so,
550 * disable load.
551 */
552 tmp = 0;
553 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
554 POWER_VDDDCTRL_DISABLE_FET);
555 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
556 POWER_VDDACTRL_DISABLE_FET);
557 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
558 POWER_VDDIOCTRL_DISABLE_FET);
559 if (tmp)
560 writel(POWER_CHARGE_ENABLE_LOAD,
561 &power_regs->hw_power_charge_clr);
562 }
563
564 /**
565 * mxs_boot_valid_5v() - Boot from 5V supply
566 *
567 * This function configures the power block to boot from valid 5V input.
568 * This is called only if the 5V is reliable and can properly supply the
569 * CPU. This function proceeds to configure the 4P2 converter to be supplied
570 * from the 5V input.
571 */
572 static void mxs_boot_valid_5v(void)
573 {
574 struct mxs_power_regs *power_regs =
575 (struct mxs_power_regs *)MXS_POWER_BASE;
576
577 /*
578 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
579 * disconnect event. FIXME
580 */
581 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
582 &power_regs->hw_power_5vctrl_set);
583
584 /* Configure polarity to check for 5V disconnection. */
585 writel(POWER_CTRL_POLARITY_VBUSVALID |
586 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
587 &power_regs->hw_power_ctrl_clr);
588
589 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
590 &power_regs->hw_power_ctrl_clr);
591
592 mxs_power_enable_4p2();
593 }
594
595 /**
596 * mxs_powerdown() - Shut down the system
597 *
598 * This function powers down the CPU completely.
599 */
600 static void mxs_powerdown(void)
601 {
602 struct mxs_power_regs *power_regs =
603 (struct mxs_power_regs *)MXS_POWER_BASE;
604 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
605 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
606 &power_regs->hw_power_reset);
607 }
608
609 /**
610 * mxs_batt_boot() - Configure the power block to boot from battery input
611 *
612 * This function configures the power block to boot from the battery voltage
613 * supply.
614 */
615 static void mxs_batt_boot(void)
616 {
617 struct mxs_power_regs *power_regs =
618 (struct mxs_power_regs *)MXS_POWER_BASE;
619
620 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
621 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
622
623 clrbits_le32(&power_regs->hw_power_dcdc4p2,
624 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
625 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
626
627 /* 5V to battery handoff. */
628 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
629 early_delay(30);
630 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
631
632 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
633
634 clrsetbits_le32(&power_regs->hw_power_minpwr,
635 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
636
637 mxs_power_set_linreg();
638
639 clrbits_le32(&power_regs->hw_power_vdddctrl,
640 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
641
642 clrbits_le32(&power_regs->hw_power_vddactrl,
643 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
644
645 clrbits_le32(&power_regs->hw_power_vddioctrl,
646 POWER_VDDIOCTRL_DISABLE_FET);
647
648 setbits_le32(&power_regs->hw_power_5vctrl,
649 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
650
651 setbits_le32(&power_regs->hw_power_5vctrl,
652 POWER_5VCTRL_ENABLE_DCDC);
653
654 clrsetbits_le32(&power_regs->hw_power_5vctrl,
655 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
656 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
657
658 mxs_power_enable_4p2();
659 }
660
661 /**
662 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
663 *
664 * This function tests if the 5V input can reliably supply the system. If it
665 * can, then proceed to configuring the system to boot from 5V source, otherwise
666 * try booting from battery supply. If we can not boot from battery supply
667 * either, shut down the system.
668 */
669 static void mxs_handle_5v_conflict(void)
670 {
671 struct mxs_power_regs *power_regs =
672 (struct mxs_power_regs *)MXS_POWER_BASE;
673 uint32_t tmp;
674
675 setbits_le32(&power_regs->hw_power_vddioctrl,
676 POWER_VDDIOCTRL_BO_OFFSET_MASK);
677
678 for (;;) {
679 tmp = readl(&power_regs->hw_power_sts);
680
681 if (tmp & POWER_STS_VDDIO_BO) {
682 /*
683 * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
684 * unreliable
685 */
686 mxs_powerdown();
687 break;
688 }
689
690 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
691 mxs_boot_valid_5v();
692 break;
693 } else {
694 mxs_powerdown();
695 break;
696 }
697
698 if (tmp & POWER_STS_PSWITCH_MASK) {
699 mxs_batt_boot();
700 break;
701 }
702 }
703 }
704
705 /**
706 * mxs_5v_boot() - Configure the power block to boot from 5V input
707 *
708 * This function handles configuration of the power block when supplied by
709 * a 5V input.
710 */
711 static void mxs_5v_boot(void)
712 {
713 struct mxs_power_regs *power_regs =
714 (struct mxs_power_regs *)MXS_POWER_BASE;
715
716 /*
717 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
718 * but their implementation always returns 1 so we omit it here.
719 */
720 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
721 mxs_boot_valid_5v();
722 return;
723 }
724
725 early_delay(1000);
726 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
727 mxs_boot_valid_5v();
728 return;
729 }
730
731 mxs_handle_5v_conflict();
732 }
733
734 /**
735 * mxs_init_batt_bo() - Configure battery brownout threshold
736 *
737 * This function configures the battery input brownout threshold. The value
738 * at which the battery brownout happens is configured to 3.0V in the code.
739 */
740 static void mxs_init_batt_bo(void)
741 {
742 struct mxs_power_regs *power_regs =
743 (struct mxs_power_regs *)MXS_POWER_BASE;
744
745 /* Brownout at 3V */
746 clrsetbits_le32(&power_regs->hw_power_battmonitor,
747 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
748 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
749
750 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
751 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
752 }
753
754 /**
755 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
756 *
757 * This function turns off the VDDD linear regulator and therefore makes
758 * the VDDD rail be supplied only by the DC-DC converter.
759 */
760 static void mxs_switch_vddd_to_dcdc_source(void)
761 {
762 struct mxs_power_regs *power_regs =
763 (struct mxs_power_regs *)MXS_POWER_BASE;
764
765 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
766 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
767 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
768
769 clrbits_le32(&power_regs->hw_power_vdddctrl,
770 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
771 POWER_VDDDCTRL_DISABLE_STEPPING);
772 }
773
774 /**
775 * mxs_power_configure_power_source() - Configure power block source
776 *
777 * This function is the core of the power configuration logic. The function
778 * selects the power block input source and configures the whole power block
779 * accordingly. After the configuration is complete and the system is stable
780 * again, the function switches the CPU clock source back to PLL. Finally,
781 * the function switches the voltage rails to DC-DC converter.
782 */
783 static void mxs_power_configure_power_source(void)
784 {
785 int batt_ready, batt_good;
786 struct mxs_power_regs *power_regs =
787 (struct mxs_power_regs *)MXS_POWER_BASE;
788 struct mxs_lradc_regs *lradc_regs =
789 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
790
791 mxs_src_power_init();
792
793 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
794 batt_ready = mxs_is_batt_ready();
795 if (batt_ready) {
796 /* 5V source detected, good battery detected. */
797 mxs_batt_boot();
798 } else {
799 batt_good = mxs_is_batt_good();
800 if (!batt_good) {
801 /* 5V source detected, bad battery detected. */
802 writel(LRADC_CONVERSION_AUTOMATIC,
803 &lradc_regs->hw_lradc_conversion_clr);
804 clrbits_le32(&power_regs->hw_power_battmonitor,
805 POWER_BATTMONITOR_BATT_VAL_MASK);
806 }
807 mxs_5v_boot();
808 }
809 } else {
810 /* 5V not detected, booting from battery. */
811 mxs_batt_boot();
812 }
813
814 mxs_power_clock2pll();
815
816 mxs_init_batt_bo();
817
818 mxs_switch_vddd_to_dcdc_source();
819
820 #ifdef CONFIG_MX23
821 /* Fire up the VDDMEM LinReg now that we're all set. */
822 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
823 &power_regs->hw_power_vddmemctrl);
824 #endif
825 }
826
827 /**
828 * mxs_enable_output_rail_protection() - Enable power rail protection
829 *
830 * This function enables overload protection on the power rails. This is
831 * triggered if the power rails' voltage drops rapidly due to overload and
832 * in such case, the supply to the powerrail is cut-off, protecting the
833 * CPU from damage. Note that under such condition, the system will likely
834 * crash or misbehave.
835 */
836 static void mxs_enable_output_rail_protection(void)
837 {
838 struct mxs_power_regs *power_regs =
839 (struct mxs_power_regs *)MXS_POWER_BASE;
840
841 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
842 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
843
844 setbits_le32(&power_regs->hw_power_vdddctrl,
845 POWER_VDDDCTRL_PWDN_BRNOUT);
846
847 setbits_le32(&power_regs->hw_power_vddactrl,
848 POWER_VDDACTRL_PWDN_BRNOUT);
849
850 setbits_le32(&power_regs->hw_power_vddioctrl,
851 POWER_VDDIOCTRL_PWDN_BRNOUT);
852 }
853
854 /**
855 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
856 *
857 * This function tests if the VDDIO rail is supplied by linear regulator
858 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
859 * returns 0 if powered by the DC-DC converter.
860 */
861 static int mxs_get_vddio_power_source_off(void)
862 {
863 struct mxs_power_regs *power_regs =
864 (struct mxs_power_regs *)MXS_POWER_BASE;
865 uint32_t tmp;
866
867 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
868 tmp = readl(&power_regs->hw_power_vddioctrl);
869 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
870 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
871 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
872 return 1;
873 }
874 }
875
876 if (!(readl(&power_regs->hw_power_5vctrl) &
877 POWER_5VCTRL_ENABLE_DCDC)) {
878 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
879 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
880 return 1;
881 }
882 }
883 }
884
885 return 0;
886
887 }
888
889 /**
890 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
891 *
892 * This function tests if the VDDD rail is supplied by linear regulator
893 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
894 * returns 0 if powered by the DC-DC converter.
895 */
896 static int mxs_get_vddd_power_source_off(void)
897 {
898 struct mxs_power_regs *power_regs =
899 (struct mxs_power_regs *)MXS_POWER_BASE;
900 uint32_t tmp;
901
902 tmp = readl(&power_regs->hw_power_vdddctrl);
903 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
904 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
905 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
906 return 1;
907 }
908 }
909
910 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
911 if (!(readl(&power_regs->hw_power_5vctrl) &
912 POWER_5VCTRL_ENABLE_DCDC)) {
913 return 1;
914 }
915 }
916
917 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
918 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
919 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
920 return 1;
921 }
922 }
923
924 return 0;
925 }
926
927 struct mxs_vddx_cfg {
928 uint32_t *reg;
929 uint8_t step_mV;
930 uint16_t lowest_mV;
931 int (*powered_by_linreg)(void);
932 uint32_t trg_mask;
933 uint32_t bo_irq;
934 uint32_t bo_enirq;
935 uint32_t bo_offset_mask;
936 uint32_t bo_offset_offset;
937 };
938
939 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
940 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
941 hw_power_vddioctrl),
942 #if defined(CONFIG_MX23)
943 .step_mV = 25,
944 #else
945 .step_mV = 50,
946 #endif
947 .lowest_mV = 2800,
948 .powered_by_linreg = mxs_get_vddio_power_source_off,
949 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
950 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
951 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
952 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
953 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
954 };
955
956 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
957 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
958 hw_power_vdddctrl),
959 .step_mV = 25,
960 .lowest_mV = 800,
961 .powered_by_linreg = mxs_get_vddd_power_source_off,
962 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
963 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
964 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
965 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
966 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
967 };
968
969 #ifdef CONFIG_MX23
970 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
971 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
972 hw_power_vddmemctrl),
973 .step_mV = 50,
974 .lowest_mV = 1700,
975 .powered_by_linreg = NULL,
976 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
977 .bo_irq = 0,
978 .bo_enirq = 0,
979 .bo_offset_mask = 0,
980 .bo_offset_offset = 0,
981 };
982 #endif
983
984 /**
985 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
986 * @cfg: Configuration data of the DC-DC converter rail
987 * @new_target: New target voltage of the DC-DC converter rail
988 * @new_brownout: New brownout trigger voltage
989 *
990 * This function configures the output voltage on the DC-DC converter rail.
991 * The rail is selected by the @cfg argument. The new voltage target is
992 * selected by the @new_target and the voltage is specified in mV. The
993 * new brownout value is selected by the @new_brownout argument and the
994 * value is also in mV.
995 */
996 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
997 uint32_t new_target, uint32_t new_brownout)
998 {
999 struct mxs_power_regs *power_regs =
1000 (struct mxs_power_regs *)MXS_POWER_BASE;
1001 uint32_t cur_target, diff, bo_int = 0;
1002 uint32_t powered_by_linreg = 0;
1003 int adjust_up, tmp;
1004
1005 new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
1006
1007 cur_target = readl(cfg->reg);
1008 cur_target &= cfg->trg_mask;
1009 cur_target *= cfg->step_mV;
1010 cur_target += cfg->lowest_mV;
1011
1012 adjust_up = new_target > cur_target;
1013 if (cfg->powered_by_linreg)
1014 powered_by_linreg = cfg->powered_by_linreg();
1015
1016 if (adjust_up && cfg->bo_irq) {
1017 if (powered_by_linreg) {
1018 bo_int = readl(cfg->reg);
1019 clrbits_le32(cfg->reg, cfg->bo_enirq);
1020 }
1021 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1022 }
1023
1024 do {
1025 if (abs(new_target - cur_target) > 100) {
1026 if (adjust_up)
1027 diff = cur_target + 100;
1028 else
1029 diff = cur_target - 100;
1030 } else {
1031 diff = new_target;
1032 }
1033
1034 diff -= cfg->lowest_mV;
1035 diff /= cfg->step_mV;
1036
1037 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1038
1039 if (powered_by_linreg ||
1040 (readl(&power_regs->hw_power_sts) &
1041 POWER_STS_VDD5V_GT_VDDIO))
1042 early_delay(500);
1043 else {
1044 for (;;) {
1045 tmp = readl(&power_regs->hw_power_sts);
1046 if (tmp & POWER_STS_DC_OK)
1047 break;
1048 }
1049 }
1050
1051 cur_target = readl(cfg->reg);
1052 cur_target &= cfg->trg_mask;
1053 cur_target *= cfg->step_mV;
1054 cur_target += cfg->lowest_mV;
1055 } while (new_target > cur_target);
1056
1057 if (cfg->bo_irq) {
1058 if (adjust_up && powered_by_linreg) {
1059 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1060 if (bo_int & cfg->bo_enirq)
1061 setbits_le32(cfg->reg, cfg->bo_enirq);
1062 }
1063
1064 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1065 new_brownout << cfg->bo_offset_offset);
1066 }
1067 }
1068
1069 /**
1070 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1071 *
1072 * This function starts and configures the LRADC block. This allows the
1073 * power initialization code to measure battery voltage and based on this
1074 * knowledge, decide whether to boot at all, boot from battery or boot
1075 * from 5V input.
1076 */
1077 static void mxs_setup_batt_detect(void)
1078 {
1079 mxs_lradc_init();
1080 mxs_lradc_enable_batt_measurement();
1081 early_delay(10);
1082 }
1083
1084 /**
1085 * mxs_ungate_power() - Ungate the POWER block
1086 *
1087 * This function ungates clock to the power block. In case the power block
1088 * was still gated at this point, it will not be possible to configure the
1089 * block and therefore the power initialization would fail. This function
1090 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1091 */
1092 static void mxs_ungate_power(void)
1093 {
1094 #ifdef CONFIG_MX23
1095 struct mxs_power_regs *power_regs =
1096 (struct mxs_power_regs *)MXS_POWER_BASE;
1097
1098 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1099 #endif
1100 }
1101
1102 /**
1103 * mxs_power_init() - The power block init main function
1104 *
1105 * This function calls all the power block initialization functions in
1106 * proper sequence to start the power block.
1107 */
1108 void mxs_power_init(void)
1109 {
1110 struct mxs_power_regs *power_regs =
1111 (struct mxs_power_regs *)MXS_POWER_BASE;
1112
1113 mxs_ungate_power();
1114
1115 mxs_power_clock2xtal();
1116 mxs_power_set_auto_restart();
1117 mxs_power_set_linreg();
1118 mxs_power_setup_5v_detect();
1119
1120 mxs_setup_batt_detect();
1121
1122 mxs_power_configure_power_source();
1123 mxs_enable_output_rail_protection();
1124
1125 mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
1126 mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
1127 #ifdef CONFIG_MX23
1128 mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
1129 #endif
1130 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1131 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1132 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1133 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1134
1135 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
1136
1137 early_delay(1000);
1138 }
1139
1140 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1141 /**
1142 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1143 *
1144 * This function waits until the power-switch was pressed to start booting
1145 * the board.
1146 */
1147 void mxs_power_wait_pswitch(void)
1148 {
1149 struct mxs_power_regs *power_regs =
1150 (struct mxs_power_regs *)MXS_POWER_BASE;
1151
1152 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1153 ;
1154 }
1155 #endif
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