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Merge branch 'master' of git://git.denx.de/u-boot-usb
[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2 * Freescale i.MX28 Boot PMIC init
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27 #include <config.h>
28 #include <asm/io.h>
29 #include <asm/arch/imx-regs.h>
30
31 #include "mxs_init.h"
32
33 static void mxs_power_clock2xtal(void)
34 {
35 struct mxs_clkctrl_regs *clkctrl_regs =
36 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
37
38 /* Set XTAL as CPU reference clock */
39 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
40 &clkctrl_regs->hw_clkctrl_clkseq_set);
41 }
42
43 static void mxs_power_clock2pll(void)
44 {
45 struct mxs_clkctrl_regs *clkctrl_regs =
46 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
47
48 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
49 CLKCTRL_PLL0CTRL0_POWER);
50 early_delay(100);
51 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
52 CLKCTRL_CLKSEQ_BYPASS_CPU);
53 }
54
55 static void mxs_power_clear_auto_restart(void)
56 {
57 struct mxs_rtc_regs *rtc_regs =
58 (struct mxs_rtc_regs *)MXS_RTC_BASE;
59
60 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
61 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
62 ;
63
64 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
65 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
66 ;
67
68 /*
69 * Due to the hardware design bug of mx28 EVK-A
70 * we need to set the AUTO_RESTART bit.
71 */
72 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
73 return;
74
75 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
76 ;
77
78 setbits_le32(&rtc_regs->hw_rtc_persistent0,
79 RTC_PERSISTENT0_AUTO_RESTART);
80 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
81 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
82 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
83 ;
84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
85 ;
86 }
87
88 static void mxs_power_set_linreg(void)
89 {
90 struct mxs_power_regs *power_regs =
91 (struct mxs_power_regs *)MXS_POWER_BASE;
92
93 /* Set linear regulator 25mV below switching converter */
94 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
95 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
96 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
97
98 clrsetbits_le32(&power_regs->hw_power_vddactrl,
99 POWER_VDDACTRL_LINREG_OFFSET_MASK,
100 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
101
102 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
103 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
104 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
105 }
106
107 static int mxs_get_batt_volt(void)
108 {
109 struct mxs_power_regs *power_regs =
110 (struct mxs_power_regs *)MXS_POWER_BASE;
111 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
112 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
113 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
114 volt *= 8;
115 return volt;
116 }
117
118 static int mxs_is_batt_ready(void)
119 {
120 return (mxs_get_batt_volt() >= 3600);
121 }
122
123 static int mxs_is_batt_good(void)
124 {
125 struct mxs_power_regs *power_regs =
126 (struct mxs_power_regs *)MXS_POWER_BASE;
127 uint32_t volt = mxs_get_batt_volt();
128
129 if ((volt >= 2400) && (volt <= 4300))
130 return 1;
131
132 clrsetbits_le32(&power_regs->hw_power_5vctrl,
133 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
134 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
135 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
136 &power_regs->hw_power_5vctrl_clr);
137
138 clrsetbits_le32(&power_regs->hw_power_charge,
139 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
140 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
141
142 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
143 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
144 &power_regs->hw_power_5vctrl_clr);
145
146 early_delay(500000);
147
148 volt = mxs_get_batt_volt();
149
150 if (volt >= 3500)
151 return 0;
152
153 if (volt >= 2400)
154 return 1;
155
156 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
157 &power_regs->hw_power_charge_clr);
158 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
159
160 return 0;
161 }
162
163 static void mxs_power_setup_5v_detect(void)
164 {
165 struct mxs_power_regs *power_regs =
166 (struct mxs_power_regs *)MXS_POWER_BASE;
167
168 /* Start 5V detection */
169 clrsetbits_le32(&power_regs->hw_power_5vctrl,
170 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
171 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
172 POWER_5VCTRL_PWRUP_VBUS_CMPS);
173 }
174
175 static void mxs_src_power_init(void)
176 {
177 struct mxs_power_regs *power_regs =
178 (struct mxs_power_regs *)MXS_POWER_BASE;
179
180 /* Improve efficieny and reduce transient ripple */
181 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
182 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
183
184 clrsetbits_le32(&power_regs->hw_power_dclimits,
185 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
186 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
187
188 setbits_le32(&power_regs->hw_power_battmonitor,
189 POWER_BATTMONITOR_EN_BATADJ);
190
191 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
192 clrsetbits_le32(&power_regs->hw_power_loopctrl,
193 POWER_LOOPCTRL_EN_RCSCALE_MASK,
194 POWER_LOOPCTRL_RCSCALE_THRESH |
195 POWER_LOOPCTRL_EN_RCSCALE_8X);
196
197 clrsetbits_le32(&power_regs->hw_power_minpwr,
198 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
199
200 /* 5V to battery handoff ... FIXME */
201 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
202 early_delay(30);
203 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
204 }
205
206 static void mxs_power_init_4p2_params(void)
207 {
208 struct mxs_power_regs *power_regs =
209 (struct mxs_power_regs *)MXS_POWER_BASE;
210
211 /* Setup 4P2 parameters */
212 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
213 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
214 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
215
216 clrsetbits_le32(&power_regs->hw_power_5vctrl,
217 POWER_5VCTRL_HEADROOM_ADJ_MASK,
218 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
219
220 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
221 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
222 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
223 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
224
225 clrsetbits_le32(&power_regs->hw_power_5vctrl,
226 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
227 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
228 }
229
230 static void mxs_enable_4p2_dcdc_input(int xfer)
231 {
232 struct mxs_power_regs *power_regs =
233 (struct mxs_power_regs *)MXS_POWER_BASE;
234 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
235 uint32_t prev_5v_brnout, prev_5v_droop;
236
237 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
238 POWER_5VCTRL_PWDN_5VBRNOUT;
239 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
240 POWER_CTRL_ENIRQ_VDD5V_DROOP;
241
242 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
243 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
244 &power_regs->hw_power_reset);
245
246 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
247
248 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
249 POWER_5VCTRL_ENABLE_DCDC)) {
250 return;
251 }
252
253 /*
254 * Recording orignal values that will be modified temporarlily
255 * to handle a chip bug. See chip errata for CQ ENGR00115837
256 */
257 tmp = readl(&power_regs->hw_power_5vctrl);
258 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
259 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
260
261 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
262
263 /*
264 * Disable mechanisms that get erroneously tripped by when setting
265 * the DCDC4P2 EN_DCDC
266 */
267 clrbits_le32(&power_regs->hw_power_5vctrl,
268 POWER_5VCTRL_VBUSVALID_5VDETECT |
269 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
270
271 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
272
273 if (xfer) {
274 setbits_le32(&power_regs->hw_power_5vctrl,
275 POWER_5VCTRL_DCDC_XFER);
276 early_delay(20);
277 clrbits_le32(&power_regs->hw_power_5vctrl,
278 POWER_5VCTRL_DCDC_XFER);
279
280 setbits_le32(&power_regs->hw_power_5vctrl,
281 POWER_5VCTRL_ENABLE_DCDC);
282 } else {
283 setbits_le32(&power_regs->hw_power_dcdc4p2,
284 POWER_DCDC4P2_ENABLE_DCDC);
285 }
286
287 early_delay(25);
288
289 clrsetbits_le32(&power_regs->hw_power_5vctrl,
290 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
291
292 if (vbus_5vdetect)
293 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
294
295 if (!pwd_bo)
296 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
297
298 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
299 writel(POWER_CTRL_VBUS_VALID_IRQ,
300 &power_regs->hw_power_ctrl_clr);
301
302 if (prev_5v_brnout) {
303 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
304 &power_regs->hw_power_5vctrl_set);
305 writel(POWER_RESET_UNLOCK_KEY,
306 &power_regs->hw_power_reset);
307 } else {
308 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
309 &power_regs->hw_power_5vctrl_clr);
310 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
311 &power_regs->hw_power_reset);
312 }
313
314 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
315 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
316 &power_regs->hw_power_ctrl_clr);
317
318 if (prev_5v_droop)
319 clrbits_le32(&power_regs->hw_power_ctrl,
320 POWER_CTRL_ENIRQ_VDD5V_DROOP);
321 else
322 setbits_le32(&power_regs->hw_power_ctrl,
323 POWER_CTRL_ENIRQ_VDD5V_DROOP);
324 }
325
326 static void mxs_power_init_4p2_regulator(void)
327 {
328 struct mxs_power_regs *power_regs =
329 (struct mxs_power_regs *)MXS_POWER_BASE;
330 uint32_t tmp, tmp2;
331
332 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
333
334 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
335
336 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
337 &power_regs->hw_power_5vctrl_clr);
338 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
339
340 /* Power up the 4p2 rail and logic/control */
341 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
342 &power_regs->hw_power_5vctrl_clr);
343
344 /*
345 * Start charging up the 4p2 capacitor. We ramp of this charge
346 * gradually to avoid large inrush current from the 5V cable which can
347 * cause transients/problems
348 */
349 mxs_enable_4p2_dcdc_input(0);
350
351 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
352 /*
353 * If we arrived here, we were unable to recover from mx23 chip
354 * errata 5837. 4P2 is disabled and sufficient battery power is
355 * not present. Exiting to not enable DCDC power during 5V
356 * connected state.
357 */
358 clrbits_le32(&power_regs->hw_power_dcdc4p2,
359 POWER_DCDC4P2_ENABLE_DCDC);
360 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
361 &power_regs->hw_power_5vctrl_set);
362 hang();
363 }
364
365 /*
366 * Here we set the 4p2 brownout level to something very close to 4.2V.
367 * We then check the brownout status. If the brownout status is false,
368 * the voltage is already close to the target voltage of 4.2V so we
369 * can go ahead and set the 4P2 current limit to our max target limit.
370 * If the brownout status is true, we need to ramp us the current limit
371 * so that we don't cause large inrush current issues. We step up the
372 * current limit until the brownout status is false or until we've
373 * reached our maximum defined 4p2 current limit.
374 */
375 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
376 POWER_DCDC4P2_BO_MASK,
377 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
378
379 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
380 setbits_le32(&power_regs->hw_power_5vctrl,
381 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
382 } else {
383 tmp = (readl(&power_regs->hw_power_5vctrl) &
384 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
385 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
386 while (tmp < 0x3f) {
387 if (!(readl(&power_regs->hw_power_sts) &
388 POWER_STS_DCDC_4P2_BO)) {
389 tmp = readl(&power_regs->hw_power_5vctrl);
390 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
391 early_delay(100);
392 writel(tmp, &power_regs->hw_power_5vctrl);
393 break;
394 } else {
395 tmp++;
396 tmp2 = readl(&power_regs->hw_power_5vctrl);
397 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
398 tmp2 |= tmp <<
399 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
400 writel(tmp2, &power_regs->hw_power_5vctrl);
401 early_delay(100);
402 }
403 }
404 }
405
406 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
407 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
408 }
409
410 static void mxs_power_init_dcdc_4p2_source(void)
411 {
412 struct mxs_power_regs *power_regs =
413 (struct mxs_power_regs *)MXS_POWER_BASE;
414
415 if (!(readl(&power_regs->hw_power_dcdc4p2) &
416 POWER_DCDC4P2_ENABLE_DCDC)) {
417 hang();
418 }
419
420 mxs_enable_4p2_dcdc_input(1);
421
422 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
423 clrbits_le32(&power_regs->hw_power_dcdc4p2,
424 POWER_DCDC4P2_ENABLE_DCDC);
425 writel(POWER_5VCTRL_ENABLE_DCDC,
426 &power_regs->hw_power_5vctrl_clr);
427 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
428 &power_regs->hw_power_5vctrl_set);
429 }
430 }
431
432 static void mxs_power_enable_4p2(void)
433 {
434 struct mxs_power_regs *power_regs =
435 (struct mxs_power_regs *)MXS_POWER_BASE;
436 uint32_t vdddctrl, vddactrl, vddioctrl;
437 uint32_t tmp;
438
439 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
440 vddactrl = readl(&power_regs->hw_power_vddactrl);
441 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
442
443 setbits_le32(&power_regs->hw_power_vdddctrl,
444 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
445 POWER_VDDDCTRL_PWDN_BRNOUT);
446
447 setbits_le32(&power_regs->hw_power_vddactrl,
448 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
449 POWER_VDDACTRL_PWDN_BRNOUT);
450
451 setbits_le32(&power_regs->hw_power_vddioctrl,
452 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
453
454 mxs_power_init_4p2_params();
455 mxs_power_init_4p2_regulator();
456
457 /* Shutdown battery (none present) */
458 if (!mxs_is_batt_ready()) {
459 clrbits_le32(&power_regs->hw_power_dcdc4p2,
460 POWER_DCDC4P2_BO_MASK);
461 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
462 &power_regs->hw_power_ctrl_clr);
463 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
464 &power_regs->hw_power_ctrl_clr);
465 }
466
467 mxs_power_init_dcdc_4p2_source();
468
469 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
470 early_delay(20);
471 writel(vddactrl, &power_regs->hw_power_vddactrl);
472 early_delay(20);
473 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
474
475 /*
476 * Check if FET is enabled on either powerout and if so,
477 * disable load.
478 */
479 tmp = 0;
480 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
481 POWER_VDDDCTRL_DISABLE_FET);
482 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
483 POWER_VDDACTRL_DISABLE_FET);
484 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
485 POWER_VDDIOCTRL_DISABLE_FET);
486 if (tmp)
487 writel(POWER_CHARGE_ENABLE_LOAD,
488 &power_regs->hw_power_charge_clr);
489 }
490
491 static void mxs_boot_valid_5v(void)
492 {
493 struct mxs_power_regs *power_regs =
494 (struct mxs_power_regs *)MXS_POWER_BASE;
495
496 /*
497 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
498 * disconnect event. FIXME
499 */
500 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
501 &power_regs->hw_power_5vctrl_set);
502
503 /* Configure polarity to check for 5V disconnection. */
504 writel(POWER_CTRL_POLARITY_VBUSVALID |
505 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
506 &power_regs->hw_power_ctrl_clr);
507
508 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
509 &power_regs->hw_power_ctrl_clr);
510
511 mxs_power_enable_4p2();
512 }
513
514 static void mxs_powerdown(void)
515 {
516 struct mxs_power_regs *power_regs =
517 (struct mxs_power_regs *)MXS_POWER_BASE;
518 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
519 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
520 &power_regs->hw_power_reset);
521 }
522
523 static void mxs_batt_boot(void)
524 {
525 struct mxs_power_regs *power_regs =
526 (struct mxs_power_regs *)MXS_POWER_BASE;
527
528 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
529 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
530
531 clrbits_le32(&power_regs->hw_power_dcdc4p2,
532 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
533 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
534
535 /* 5V to battery handoff. */
536 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
537 early_delay(30);
538 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
539
540 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
541
542 clrsetbits_le32(&power_regs->hw_power_minpwr,
543 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
544
545 mxs_power_set_linreg();
546
547 clrbits_le32(&power_regs->hw_power_vdddctrl,
548 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
549
550 clrbits_le32(&power_regs->hw_power_vddactrl,
551 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
552
553 clrbits_le32(&power_regs->hw_power_vddioctrl,
554 POWER_VDDIOCTRL_DISABLE_FET);
555
556 setbits_le32(&power_regs->hw_power_5vctrl,
557 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
558
559 setbits_le32(&power_regs->hw_power_5vctrl,
560 POWER_5VCTRL_ENABLE_DCDC);
561
562 clrsetbits_le32(&power_regs->hw_power_5vctrl,
563 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
564 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
565 }
566
567 static void mxs_handle_5v_conflict(void)
568 {
569 struct mxs_power_regs *power_regs =
570 (struct mxs_power_regs *)MXS_POWER_BASE;
571 uint32_t tmp;
572
573 setbits_le32(&power_regs->hw_power_vddioctrl,
574 POWER_VDDIOCTRL_BO_OFFSET_MASK);
575
576 for (;;) {
577 tmp = readl(&power_regs->hw_power_sts);
578
579 if (tmp & POWER_STS_VDDIO_BO) {
580 /*
581 * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
582 * unreliable
583 */
584 mxs_powerdown();
585 break;
586 }
587
588 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
589 mxs_boot_valid_5v();
590 break;
591 } else {
592 mxs_powerdown();
593 break;
594 }
595
596 if (tmp & POWER_STS_PSWITCH_MASK) {
597 mxs_batt_boot();
598 break;
599 }
600 }
601 }
602
603 static void mxs_5v_boot(void)
604 {
605 struct mxs_power_regs *power_regs =
606 (struct mxs_power_regs *)MXS_POWER_BASE;
607
608 /*
609 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
610 * but their implementation always returns 1 so we omit it here.
611 */
612 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
613 mxs_boot_valid_5v();
614 return;
615 }
616
617 early_delay(1000);
618 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
619 mxs_boot_valid_5v();
620 return;
621 }
622
623 mxs_handle_5v_conflict();
624 }
625
626 static void mxs_init_batt_bo(void)
627 {
628 struct mxs_power_regs *power_regs =
629 (struct mxs_power_regs *)MXS_POWER_BASE;
630
631 /* Brownout at 3V */
632 clrsetbits_le32(&power_regs->hw_power_battmonitor,
633 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
634 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
635
636 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
637 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
638 }
639
640 static void mxs_switch_vddd_to_dcdc_source(void)
641 {
642 struct mxs_power_regs *power_regs =
643 (struct mxs_power_regs *)MXS_POWER_BASE;
644
645 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
646 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
647 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
648
649 clrbits_le32(&power_regs->hw_power_vdddctrl,
650 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
651 POWER_VDDDCTRL_DISABLE_STEPPING);
652 }
653
654 static void mxs_power_configure_power_source(void)
655 {
656 int batt_ready, batt_good;
657 struct mxs_power_regs *power_regs =
658 (struct mxs_power_regs *)MXS_POWER_BASE;
659 struct mxs_lradc_regs *lradc_regs =
660 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
661
662 mxs_src_power_init();
663
664 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
665 batt_ready = mxs_is_batt_ready();
666 if (batt_ready) {
667 /* 5V source detected, good battery detected. */
668 mxs_batt_boot();
669 } else {
670 batt_good = mxs_is_batt_good();
671 if (!batt_good) {
672 /* 5V source detected, bad battery detected. */
673 writel(LRADC_CONVERSION_AUTOMATIC,
674 &lradc_regs->hw_lradc_conversion_clr);
675 clrbits_le32(&power_regs->hw_power_battmonitor,
676 POWER_BATTMONITOR_BATT_VAL_MASK);
677 }
678 mxs_5v_boot();
679 }
680 } else {
681 /* 5V not detected, booting from battery. */
682 mxs_batt_boot();
683 }
684
685 mxs_power_clock2pll();
686
687 mxs_init_batt_bo();
688
689 mxs_switch_vddd_to_dcdc_source();
690 }
691
692 static void mxs_enable_output_rail_protection(void)
693 {
694 struct mxs_power_regs *power_regs =
695 (struct mxs_power_regs *)MXS_POWER_BASE;
696
697 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
698 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
699
700 setbits_le32(&power_regs->hw_power_vdddctrl,
701 POWER_VDDDCTRL_PWDN_BRNOUT);
702
703 setbits_le32(&power_regs->hw_power_vddactrl,
704 POWER_VDDACTRL_PWDN_BRNOUT);
705
706 setbits_le32(&power_regs->hw_power_vddioctrl,
707 POWER_VDDIOCTRL_PWDN_BRNOUT);
708 }
709
710 static int mxs_get_vddio_power_source_off(void)
711 {
712 struct mxs_power_regs *power_regs =
713 (struct mxs_power_regs *)MXS_POWER_BASE;
714 uint32_t tmp;
715
716 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
717 tmp = readl(&power_regs->hw_power_vddioctrl);
718 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
719 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
720 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
721 return 1;
722 }
723 }
724
725 if (!(readl(&power_regs->hw_power_5vctrl) &
726 POWER_5VCTRL_ENABLE_DCDC)) {
727 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
728 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
729 return 1;
730 }
731 }
732 }
733
734 return 0;
735
736 }
737
738 static int mxs_get_vddd_power_source_off(void)
739 {
740 struct mxs_power_regs *power_regs =
741 (struct mxs_power_regs *)MXS_POWER_BASE;
742 uint32_t tmp;
743
744 tmp = readl(&power_regs->hw_power_vdddctrl);
745 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
746 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
747 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
748 return 1;
749 }
750 }
751
752 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
753 if (!(readl(&power_regs->hw_power_5vctrl) &
754 POWER_5VCTRL_ENABLE_DCDC)) {
755 return 1;
756 }
757 }
758
759 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
760 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
761 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
762 return 1;
763 }
764 }
765
766 return 0;
767 }
768
769 struct mxs_vddx_cfg {
770 uint32_t *reg;
771 uint8_t step_mV;
772 uint16_t lowest_mV;
773 int (*powered_by_linreg)(void);
774 uint32_t trg_mask;
775 uint32_t bo_irq;
776 uint32_t bo_enirq;
777 uint32_t bo_offset_mask;
778 uint32_t bo_offset_offset;
779 };
780
781 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
782 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
783 hw_power_vddioctrl),
784 .step_mV = 50,
785 .lowest_mV = 2800,
786 .powered_by_linreg = mxs_get_vddio_power_source_off,
787 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
788 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
789 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
790 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
791 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
792 };
793
794 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
795 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
796 hw_power_vdddctrl),
797 .step_mV = 25,
798 .lowest_mV = 800,
799 .powered_by_linreg = mxs_get_vddd_power_source_off,
800 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
801 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
802 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
803 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
804 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
805 };
806
807 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
808 uint32_t new_target, uint32_t new_brownout)
809 {
810 struct mxs_power_regs *power_regs =
811 (struct mxs_power_regs *)MXS_POWER_BASE;
812 uint32_t cur_target, diff, bo_int = 0;
813 uint32_t powered_by_linreg = 0;
814 int adjust_up, tmp;
815
816 new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
817
818 cur_target = readl(cfg->reg);
819 cur_target &= cfg->trg_mask;
820 cur_target *= cfg->step_mV;
821 cur_target += cfg->lowest_mV;
822
823 adjust_up = new_target > cur_target;
824 powered_by_linreg = cfg->powered_by_linreg();
825
826 if (adjust_up) {
827 if (powered_by_linreg) {
828 bo_int = readl(cfg->reg);
829 clrbits_le32(cfg->reg, cfg->bo_enirq);
830 }
831 setbits_le32(cfg->reg, cfg->bo_offset_mask);
832 }
833
834 do {
835 if (abs(new_target - cur_target) > 100) {
836 if (adjust_up)
837 diff = cur_target + 100;
838 else
839 diff = cur_target - 100;
840 } else {
841 diff = new_target;
842 }
843
844 diff -= cfg->lowest_mV;
845 diff /= cfg->step_mV;
846
847 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
848
849 if (powered_by_linreg ||
850 (readl(&power_regs->hw_power_sts) &
851 POWER_STS_VDD5V_GT_VDDIO))
852 early_delay(500);
853 else {
854 for (;;) {
855 tmp = readl(&power_regs->hw_power_sts);
856 if (tmp & POWER_STS_DC_OK)
857 break;
858 }
859 }
860
861 cur_target = readl(cfg->reg);
862 cur_target &= cfg->trg_mask;
863 cur_target *= cfg->step_mV;
864 cur_target += cfg->lowest_mV;
865 } while (new_target > cur_target);
866
867 if (adjust_up && powered_by_linreg) {
868 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
869 if (bo_int & cfg->bo_enirq)
870 setbits_le32(cfg->reg, cfg->bo_enirq);
871 }
872
873 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
874 new_brownout << cfg->bo_offset_offset);
875 }
876
877 static void mxs_setup_batt_detect(void)
878 {
879 mxs_lradc_init();
880 mxs_lradc_enable_batt_measurement();
881 early_delay(10);
882 }
883
884 static void mxs_ungate_power(void)
885 {
886 #ifdef CONFIG_MX23
887 struct mxs_power_regs *power_regs =
888 (struct mxs_power_regs *)MXS_POWER_BASE;
889
890 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
891 #endif
892 }
893
894 void mxs_power_init(void)
895 {
896 struct mxs_power_regs *power_regs =
897 (struct mxs_power_regs *)MXS_POWER_BASE;
898
899 mxs_ungate_power();
900
901 mxs_power_clock2xtal();
902 mxs_power_clear_auto_restart();
903 mxs_power_set_linreg();
904 mxs_power_setup_5v_detect();
905
906 mxs_setup_batt_detect();
907
908 mxs_power_configure_power_source();
909 mxs_enable_output_rail_protection();
910
911 mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
912 mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
913
914 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
915 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
916 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
917 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
918
919 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
920
921 early_delay(1000);
922 }
923
924 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
925 void mxs_power_wait_pswitch(void)
926 {
927 struct mxs_power_regs *power_regs =
928 (struct mxs_power_regs *)MXS_POWER_BASE;
929
930 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
931 ;
932 }
933 #endif
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