arch/arm/cpu/arm926ejs/orion5x/dram.c

   1 /*
   2  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
   3  *
   4  * Based on original Kirkwood support which is
   5  * (C) Copyright 2009
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <config.h>
  14 #include <asm/arch/cpu.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 /*
  19  * orion5x_sdram_bar - reads SDRAM Base Address Register
  20  */
  21 u32 orion5x_sdram_bar(enum memory_bank bank)
  22 {
  23         struct orion5x_ddr_addr_decode_registers *winregs =
  24                 (struct orion5x_ddr_addr_decode_registers *)
  25                 ORION5X_DRAM_BASE;
  26
  27         u32 result = 0;
  28         u32 enable = 0x01 & winregs[bank].size;
  29
  30         if ((!enable) || (bank > BANK3))
  31                 return 0;
  32
  33         result = winregs[bank].base;
  34         return result;
  35 }
  36 int dram_init (void)
  37 {
  38         /* dram_init must store complete ramsize in gd->ram_size */
  39         gd->ram_size = get_ram_size(
  40                         (long *) orion5x_sdram_bar(0),
  41                         CONFIG_MAX_RAM_BANK_SIZE);
  42         return 0;
  43 }
  44
  45 void dram_init_banksize (void)
  46 {
  47         int i;
  48
  49         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  50                 gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
  51                 gd->bd->bi_dram[i].size = get_ram_size(
  52                         (long *) (gd->bd->bi_dram[i].start),
  53                         CONFIG_MAX_RAM_BANK_SIZE);
  54         }
  55 }