arch/arm/cpu/arm926ejs/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #include <asm-offsets.h>
  35 #include <config.h>
  36 #include <common.h>
  37 #include <version.h>
  38
  39 #if defined(CONFIG_OMAP1610)
  40 #include <./configs/omap1510.h>
  41 #elif defined(CONFIG_OMAP730)
  42 #include <./configs/omap730.h>
  43 #endif
  44
  45 /*
  46  *************************************************************************
  47  *
  48  * Jump vector table as in table 3.1 in [1]
  49  *
  50  *************************************************************************
  51  */
  52
  53
  54 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
  55 .globl _start
  56 _start:
  57 .globl _NOR_BOOT_CFG
  58 _NOR_BOOT_CFG:
  59         .word   CONFIG_SYS_DV_NOR_BOOT_CFG
  60         b       reset
  61 #else
  62 .globl _start
  63 _start:
  64         b       reset
  65 #endif
  66 #ifdef CONFIG_SPL_BUILD
  67 /* No exception handlers in preloader */
  68         ldr     pc, _hang
  69         ldr     pc, _hang
  70         ldr     pc, _hang
  71         ldr     pc, _hang
  72         ldr     pc, _hang
  73         ldr     pc, _hang
  74         ldr     pc, _hang
  75
  76 _hang:
  77         .word   do_hang
  78 /* pad to 64 byte boundary */
  79         .word   0x12345678
  80         .word   0x12345678
  81         .word   0x12345678
  82         .word   0x12345678
  83         .word   0x12345678
  84         .word   0x12345678
  85         .word   0x12345678
  86 #else
  87         ldr     pc, _undefined_instruction
  88         ldr     pc, _software_interrupt
  89         ldr     pc, _prefetch_abort
  90         ldr     pc, _data_abort
  91         ldr     pc, _not_used
  92         ldr     pc, _irq
  93         ldr     pc, _fiq
  94
  95 _undefined_instruction:
  96         .word undefined_instruction
  97 _software_interrupt:
  98         .word software_interrupt
  99 _prefetch_abort:
 100         .word prefetch_abort
 101 _data_abort:
 102         .word data_abort
 103 _not_used:
 104         .word not_used
 105 _irq:
 106         .word irq
 107 _fiq:
 108         .word fiq
 109
 110 #endif  /* CONFIG_SPL_BUILD */
 111         .balignl 16,0xdeadbeef
 112
 113
 114 /*
 115  *************************************************************************
 116  *
 117  * Startup Code (reset vector)
 118  *
 119  * do important init only if we don't start from memory!
 120  * setup Memory and board specific bits prior to relocation.
 121  * relocate armboot to ram
 122  * setup stack
 123  *
 124  *************************************************************************
 125  */
 126
 127 .globl _TEXT_BASE
 128 _TEXT_BASE:
 129 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
 130         .word   CONFIG_SYS_TEXT_BASE
 131 #else
 132 #ifdef CONFIG_SPL_BUILD
 133         .word   CONFIG_SPL_TEXT_BASE
 134 #else
 135         .word   CONFIG_SYS_TEXT_BASE
 136 #endif
 137 #endif
 138
 139 /*
 140  * These are defined in the board-specific linker script.
 141  * Subtracting _start from them lets the linker put their
 142  * relative position in the executable instead of leaving
 143  * them null.
 144  */
 145 .globl _bss_start_ofs
 146 _bss_start_ofs:
 147         .word __bss_start - _start
 148
 149 .globl _bss_end_ofs
 150 _bss_end_ofs:
 151         .word __bss_end__ - _start
 152
 153 .globl _end_ofs
 154 _end_ofs:
 155         .word _end - _start
 156
 157 #ifdef CONFIG_NAND_U_BOOT
 158 .globl _end
 159 _end:
 160         .word __bss_end__
 161 #endif
 162
 163 #ifdef CONFIG_USE_IRQ
 164 /* IRQ stack memory (calculated at run-time) */
 165 .globl IRQ_STACK_START
 166 IRQ_STACK_START:
 167         .word   0x0badc0de
 168
 169 /* IRQ stack memory (calculated at run-time) */
 170 .globl FIQ_STACK_START
 171 FIQ_STACK_START:
 172         .word 0x0badc0de
 173 #endif
 174
 175 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 176 .globl IRQ_STACK_START_IN
 177 IRQ_STACK_START_IN:
 178         .word   0x0badc0de
 179
 180 /*
 181  * the actual reset code
 182  */
 183
 184 reset:
 185         /*
 186          * set the cpu to SVC32 mode
 187          */
 188         mrs     r0,cpsr
 189         bic     r0,r0,#0x1f
 190         orr     r0,r0,#0xd3
 191         msr     cpsr,r0
 192
 193         /*
 194          * we do sys-critical inits only at reboot,
 195          * not when booting from ram!
 196          */
 197 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 198         bl      cpu_init_crit
 199 #endif
 200
 201         bl      _main
 202
 203 /*------------------------------------------------------------------------------*/
 204
 205 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
 206 /*
 207  * void relocate_code (addr_sp, gd, addr_moni)
 208  *
 209  * This "function" does not return, instead it continues in RAM
 210  * after relocating the monitor code.
 211  *
 212  */
 213         .globl  relocate_code
 214 relocate_code:
 215         mov     r4, r0  /* save addr_sp */
 216         mov     r5, r1  /* save addr of gd */
 217         mov     r6, r2  /* save addr of destination */
 218
 219         adr     r0, _start
 220         sub     r9, r6, r0              /* r9 <- relocation offset */
 221         cmp     r0, r6
 222         moveq   r9, #0                  /* no relocation. offset(r9) = 0 */
 223         beq     relocate_done           /* skip relocation */
 224         mov     r1, r6                  /* r1 <- scratch for copy loop */
 225         ldr     r3, _bss_start_ofs
 226         add     r2, r0, r3              /* r2 <- source end address         */
 227
 228 copy_loop:
 229         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 230         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 231         cmp     r0, r2                  /* until source end address [r2]    */
 232         blo     copy_loop
 233
 234 #ifndef CONFIG_SPL_BUILD
 235         /*
 236          * fix .rel.dyn relocations
 237          */
 238         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 239         sub     r9, r6, r0              /* r9 <- relocation offset */
 240         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 241         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 242         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 243         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 244         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 245         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 246 fixloop:
 247         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 248         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 249         ldr     r1, [r2, #4]
 250         and     r7, r1, #0xff
 251         cmp     r7, #23                 /* relative fixup? */
 252         beq     fixrel
 253         cmp     r7, #2                  /* absolute fixup? */
 254         beq     fixabs
 255         /* ignore unknown type of fixup */
 256         b       fixnext
 257 fixabs:
 258         /* absolute fix: set location to (offset) symbol value */
 259         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 260         add     r1, r10, r1             /* r1 <- address of symbol in table */
 261         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 262         add     r1, r1, r9              /* r1 <- relocated sym addr */
 263         b       fixnext
 264 fixrel:
 265         /* relative fix: increase location by offset */
 266         ldr     r1, [r0]
 267         add     r1, r1, r9
 268 fixnext:
 269         str     r1, [r0]
 270         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 271         cmp     r2, r3
 272         blo     fixloop
 273 #endif
 274
 275 relocate_done:
 276
 277         bx      lr
 278
 279 _rel_dyn_start_ofs:
 280         .word __rel_dyn_start - _start
 281 _rel_dyn_end_ofs:
 282         .word __rel_dyn_end - _start
 283 _dynsym_start_ofs:
 284         .word __dynsym_start - _start
 285
 286 #endif
 287
 288         .globl  c_runtime_cpu_setup
 289 c_runtime_cpu_setup:
 290
 291         bx      lr
 292
 293 /*
 294  *************************************************************************
 295  *
 296  * CPU_init_critical registers
 297  *
 298  * setup important registers
 299  * setup memory timing
 300  *
 301  *************************************************************************
 302  */
 303 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 304 cpu_init_crit:
 305         /*
 306          * flush D cache before disabling it
 307          */
 308         mov     r0, #0
 309 flush_dcache:
 310         mrc     p15, 0, r15, c7, c10, 3
 311         bne     flush_dcache
 312
 313         mcr     p15, 0, r0, c8, c7, 0   /* invalidate TLB */
 314         mcr     p15, 0, r0, c7, c5, 0   /* invalidate I Cache */
 315
 316         /*
 317          * disable MMU and D cache
 318          * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
 319          */
 320         mrc     p15, 0, r0, c1, c0, 0
 321         bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
 322         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
 323 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 324         orr     r0, r0, #0x00002000     /* set bit 13 (--V- ----) */
 325 #else
 326         bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
 327 #endif
 328         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 329 #ifndef CONFIG_SYS_ICACHE_OFF
 330         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 331 #endif
 332         mcr     p15, 0, r0, c1, c0, 0
 333
 334         /*
 335          * Go setup Memory and board specific bits prior to relocation.
 336          */
 337         mov     ip, lr          /* perserve link reg across call */
 338         bl      lowlevel_init   /* go setup pll,mux,memory */
 339         mov     lr, ip          /* restore link */
 340         mov     pc, lr          /* back to my caller */
 341 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 342
 343 #ifndef CONFIG_SPL_BUILD
 344 /*
 345  *************************************************************************
 346  *
 347  * Interrupt handling
 348  *
 349  *************************************************************************
 350  */
 351
 352 @
 353 @ IRQ stack frame.
 354 @
 355 #define S_FRAME_SIZE    72
 356
 357 #define S_OLD_R0        68
 358 #define S_PSR           64
 359 #define S_PC            60
 360 #define S_LR            56
 361 #define S_SP            52
 362
 363 #define S_IP            48
 364 #define S_FP            44
 365 #define S_R10           40
 366 #define S_R9            36
 367 #define S_R8            32
 368 #define S_R7            28
 369 #define S_R6            24
 370 #define S_R5            20
 371 #define S_R4            16
 372 #define S_R3            12
 373 #define S_R2            8
 374 #define S_R1            4
 375 #define S_R0            0
 376
 377 #define MODE_SVC 0x13
 378 #define I_BIT    0x80
 379
 380 /*
 381  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 382  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 383  */
 384
 385         .macro  bad_save_user_regs
 386         @ carve out a frame on current user stack
 387         sub     sp, sp, #S_FRAME_SIZE
 388         stmia   sp, {r0 - r12}  @ Save user registers (now in svc mode) r0-r12
 389         ldr     r2, IRQ_STACK_START_IN
 390         @ get values for "aborted" pc and cpsr (into parm regs)
 391         ldmia   r2, {r2 - r3}
 392         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 393         add     r5, sp, #S_SP
 394         mov     r1, lr
 395         stmia   r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
 396         mov     r0, sp          @ save current stack into r0 (param register)
 397         .endm
 398
 399         .macro  irq_save_user_regs
 400         sub     sp, sp, #S_FRAME_SIZE
 401         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 402         @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 403         add     r8, sp, #S_PC
 404         stmdb   r8, {sp, lr}^           @ Calling SP, LR
 405         str     lr, [r8, #0]            @ Save calling PC
 406         mrs     r6, spsr
 407         str     r6, [r8, #4]            @ Save CPSR
 408         str     r0, [r8, #8]            @ Save OLD_R0
 409         mov     r0, sp
 410         .endm
 411
 412         .macro  irq_restore_user_regs
 413         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 414         mov     r0, r0
 415         ldr     lr, [sp, #S_PC]                 @ Get PC
 416         add     sp, sp, #S_FRAME_SIZE
 417         subs    pc, lr, #4              @ return & move spsr_svc into cpsr
 418         .endm
 419
 420         .macro get_bad_stack
 421         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 422
 423         str     lr, [r13]       @ save caller lr in position 0 of saved stack
 424         mrs     lr, spsr        @ get the spsr
 425         str     lr, [r13, #4]   @ save spsr in position 1 of saved stack
 426         mov     r13, #MODE_SVC  @ prepare SVC-Mode
 427         @ msr   spsr_c, r13
 428         msr     spsr, r13       @ switch modes, make sure moves will execute
 429         mov     lr, pc          @ capture return pc
 430         movs    pc, lr          @ jump to next instruction & switch modes.
 431         .endm
 432
 433         .macro get_irq_stack                    @ setup IRQ stack
 434         ldr     sp, IRQ_STACK_START
 435         .endm
 436
 437         .macro get_fiq_stack                    @ setup FIQ stack
 438         ldr     sp, FIQ_STACK_START
 439         .endm
 440 #endif  /* CONFIG_SPL_BUILD */
 441
 442 /*
 443  * exception handlers
 444  */
 445 #ifdef CONFIG_SPL_BUILD
 446         .align  5
 447 do_hang:
 448         ldr     sp, _TEXT_BASE                  /* switch to abort stack */
 449 1:
 450         bl      1b                              /* hang and never return */
 451 #else   /* !CONFIG_SPL_BUILD */
 452         .align  5
 453 undefined_instruction:
 454         get_bad_stack
 455         bad_save_user_regs
 456         bl      do_undefined_instruction
 457
 458         .align  5
 459 software_interrupt:
 460         get_bad_stack
 461         bad_save_user_regs
 462         bl      do_software_interrupt
 463
 464         .align  5
 465 prefetch_abort:
 466         get_bad_stack
 467         bad_save_user_regs
 468         bl      do_prefetch_abort
 469
 470         .align  5
 471 data_abort:
 472         get_bad_stack
 473         bad_save_user_regs
 474         bl      do_data_abort
 475
 476         .align  5
 477 not_used:
 478         get_bad_stack
 479         bad_save_user_regs
 480         bl      do_not_used
 481
 482 #ifdef CONFIG_USE_IRQ
 483
 484         .align  5
 485 irq:
 486         get_irq_stack
 487         irq_save_user_regs
 488         bl      do_irq
 489         irq_restore_user_regs
 490
 491         .align  5
 492 fiq:
 493         get_fiq_stack
 494         /* someone ought to write a more effiction fiq_save_user_regs */
 495         irq_save_user_regs
 496         bl      do_fiq
 497         irq_restore_user_regs
 498
 499 #else
 500
 501         .align  5
 502 irq:
 503         get_bad_stack
 504         bad_save_user_regs
 505         bl      do_irq
 506
 507         .align  5
 508 fiq:
 509         get_bad_stack
 510         bad_save_user_regs
 511         bl      do_fiq
 512
 513 #endif
 514 #endif  /* CONFIG_SPL_BUILD */