arch/arm/cpu/arm946es/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *  Copyright (c) 2010  Albert Aribaud <albert.aribaud@free.fr>
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #include <asm-offsets.h>
  35 #include <config.h>
  36 #include <version.h>
  37
  38 /*
  39  *************************************************************************
  40  *
  41  * Jump vector table as in table 3.1 in [1]
  42  *
  43  *************************************************************************
  44  */
  45
  46
  47 .globl _start
  48 _start:
  49         b       reset
  50         ldr     pc, _undefined_instruction
  51         ldr     pc, _software_interrupt
  52         ldr     pc, _prefetch_abort
  53         ldr     pc, _data_abort
  54         ldr     pc, _not_used
  55         ldr     pc, _irq
  56         ldr     pc, _fiq
  57
  58 _undefined_instruction:
  59         .word undefined_instruction
  60 _software_interrupt:
  61         .word software_interrupt
  62 _prefetch_abort:
  63         .word prefetch_abort
  64 _data_abort:
  65         .word data_abort
  66 _not_used:
  67         .word not_used
  68 _irq:
  69         .word irq
  70 _fiq:
  71         .word fiq
  72
  73         .balignl 16,0xdeadbeef
  74
  75 _vectors_end:
  76
  77 /*
  78  *************************************************************************
  79  *
  80  * Startup Code (reset vector)
  81  *
  82  * do important init only if we don't start from memory!
  83  * setup Memory and board specific bits prior to relocation.
  84  * relocate armboot to ram
  85  * setup stack
  86  *
  87  *************************************************************************
  88  */
  89
  90 .globl _TEXT_BASE
  91 _TEXT_BASE:
  92         .word   CONFIG_SYS_TEXT_BASE
  93
  94 /*
  95  * These are defined in the board-specific linker script.
  96  * Subtracting _start from them lets the linker put their
  97  * relative position in the executable instead of leaving
  98  * them null.
  99  */
 100 .globl _bss_start_ofs
 101 _bss_start_ofs:
 102         .word __bss_start - _start
 103
 104 .globl _bss_end_ofs
 105 _bss_end_ofs:
 106         .word _end - _start
 107
 108 #ifdef CONFIG_USE_IRQ
 109 /* IRQ stack memory (calculated at run-time) */
 110 .globl IRQ_STACK_START
 111 IRQ_STACK_START:
 112         .word   0x0badc0de
 113
 114 /* IRQ stack memory (calculated at run-time) */
 115 .globl FIQ_STACK_START
 116 FIQ_STACK_START:
 117         .word 0x0badc0de
 118 #endif
 119
 120 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 121 .globl IRQ_STACK_START_IN
 122 IRQ_STACK_START_IN:
 123         .word   0x0badc0de
 124
 125 /*
 126  * the actual reset code
 127  */
 128
 129 reset:
 130         /*
 131          * set the cpu to SVC32 mode
 132          */
 133         mrs     r0,cpsr
 134         bic     r0,r0,#0x1f
 135         orr     r0,r0,#0xd3
 136         msr     cpsr,r0
 137
 138         /*
 139          * we do sys-critical inits only at reboot,
 140          * not when booting from ram!
 141          */
 142 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 143         bl      cpu_init_crit
 144 #endif
 145
 146 /* Set stackpointer in internal RAM to call board_init_f */
 147 call_board_init_f:
 148         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 149         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 150         ldr     r0,=0x00000000
 151         bl      board_init_f
 152
 153 /*------------------------------------------------------------------------------*/
 154
 155 /*
 156  * void relocate_code (addr_sp, gd, addr_moni)
 157  *
 158  * This "function" does not return, instead it continues in RAM
 159  * after relocating the monitor code.
 160  *
 161  */
 162         .globl  relocate_code
 163 relocate_code:
 164         mov     r4, r0  /* save addr_sp */
 165         mov     r5, r1  /* save addr of gd */
 166         mov     r6, r2  /* save addr of destination */
 167         mov     r7, r2  /* save addr of destination */
 168
 169         /* Set up the stack                                                 */
 170 stack_setup:
 171         mov     sp, r4
 172
 173         adr     r0, _start
 174         ldr     r2, _TEXT_BASE
 175         ldr     r3, _bss_start_ofs
 176         add     r2, r0, r3              /* r2 <- source end address         */
 177         cmp     r0, r6
 178         beq     clear_bss
 179
 180 copy_loop:
 181         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 182         stmia   r6!, {r9-r10}           /* copy to   target address [r1]    */
 183         cmp     r0, r2                  /* until source end address [r2]    */
 184         blo     copy_loop
 185
 186 #ifndef CONFIG_PRELOADER
 187         /*
 188          * fix .rel.dyn relocations
 189          */
 190         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 191         sub     r9, r7, r0              /* r9 <- relocation offset */
 192         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 193         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 194         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 195         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 196         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 197         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 198 fixloop:
 199         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 200         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 201         ldr     r1, [r2, #4]
 202         and     r8, r1, #0xff
 203         cmp     r8, #23                 /* relative fixup? */
 204         beq     fixrel
 205         cmp     r8, #2                  /* absolute fixup? */
 206         beq     fixabs
 207         /* ignore unknown type of fixup */
 208         b       fixnext
 209 fixabs:
 210         /* absolute fix: set location to (offset) symbol value */
 211         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 212         add     r1, r10, r1             /* r1 <- address of symbol in table */
 213         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 214         add     r1, r9                  /* r1 <- relocated sym addr */
 215         b       fixnext
 216 fixrel:
 217         /* relative fix: increase location by offset */
 218         ldr     r1, [r0]
 219         add     r1, r1, r9
 220 fixnext:
 221         str     r1, [r0]
 222         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 223         cmp     r2, r3
 224         blo     fixloop
 225 #endif
 226
 227 clear_bss:
 228 #ifndef CONFIG_PRELOADER
 229         ldr     r0, _bss_start_ofs
 230         ldr     r1, _bss_end_ofs
 231         ldr     r3, _TEXT_BASE          /* Text base */
 232         mov     r4, r7                  /* reloc addr */
 233         add     r0, r0, r4
 234         add     r1, r1, r4
 235         mov     r2, #0x00000000         /* clear                            */
 236
 237 clbss_l:str     r2, [r0]                /* clear loop...                    */
 238         add     r0, r0, #4
 239         cmp     r0, r1
 240         blo     clbss_l
 241 #endif
 242
 243 /*
 244  * We are done. Do not return, instead branch to second part of board
 245  * initialization, now running from RAM.
 246  */
 247 #ifdef CONFIG_NAND_SPL
 248         ldr     pc, _nand_boot
 249
 250 _nand_boot: .word nand_boot
 251 #else
 252         ldr     r0, _board_init_r_ofs
 253         adr     r1, _start
 254         add     lr, r0, r1
 255         add     lr, lr, r9
 256         /* setup parameters for board_init_r */
 257         mov     r0, r5          /* gd_t */
 258         mov     r1, r7          /* dest_addr */
 259         /* jump to it ... */
 260         mov     pc, lr
 261
 262 _board_init_r_ofs:
 263         .word board_init_r - _start
 264 #endif
 265
 266 _rel_dyn_start_ofs:
 267         .word __rel_dyn_start - _start
 268 _rel_dyn_end_ofs:
 269         .word __rel_dyn_end - _start
 270 _dynsym_start_ofs:
 271         .word __dynsym_start - _start
 272
 273 /*
 274  *************************************************************************
 275  *
 276  * CPU_init_critical registers
 277  *
 278  * setup important registers
 279  * setup memory timing
 280  *
 281  *************************************************************************
 282  */
 283
 284
 285 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 286 cpu_init_crit:
 287         /*
 288          * flush v4 I/D caches
 289          */
 290         mov     r0, #0
 291         mcr     p15, 0, r0, c7, c5, 0   /* flush v4 I-cache */
 292         mcr     p15, 0, r0, c7, c6, 0   /* flush v4 D-cache */
 293
 294         /*
 295          * disable MMU stuff and caches
 296          */
 297         mrc     p15, 0, r0, c1, c0, 0
 298         bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
 299         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
 300         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 301         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 302         mcr     p15, 0, r0, c1, c0, 0
 303
 304         /*
 305          * Go setup Memory and board specific bits prior to relocation.
 306          */
 307         mov     ip, lr          /* perserve link reg across call */
 308         bl      lowlevel_init   /* go setup memory */
 309         mov     lr, ip          /* restore link */
 310         mov     pc, lr          /* back to my caller */
 311 #endif
 312 /*
 313  *************************************************************************
 314  *
 315  * Interrupt handling
 316  *
 317  *************************************************************************
 318  */
 319
 320 @
 321 @ IRQ stack frame.
 322 @
 323 #define S_FRAME_SIZE    72
 324
 325 #define S_OLD_R0        68
 326 #define S_PSR           64
 327 #define S_PC            60
 328 #define S_LR            56
 329 #define S_SP            52
 330
 331 #define S_IP            48
 332 #define S_FP            44
 333 #define S_R10           40
 334 #define S_R9            36
 335 #define S_R8            32
 336 #define S_R7            28
 337 #define S_R6            24
 338 #define S_R5            20
 339 #define S_R4            16
 340 #define S_R3            12
 341 #define S_R2            8
 342 #define S_R1            4
 343 #define S_R0            0
 344
 345 #define MODE_SVC 0x13
 346 #define I_BIT    0x80
 347
 348 /*
 349  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 350  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 351  */
 352
 353         .macro  bad_save_user_regs
 354         @ carve out a frame on current user stack
 355         sub     sp, sp, #S_FRAME_SIZE
 356         stmia   sp, {r0 - r12}  @ Save user registers (now in svc mode) r0-r12
 357
 358         ldr     r2, IRQ_STACK_START_IN
 359         @ get values for "aborted" pc and cpsr (into parm regs)
 360         ldmia   r2, {r2 - r3}
 361         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 362         add     r5, sp, #S_SP
 363         mov     r1, lr
 364         stmia   r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
 365         mov     r0, sp          @ save current stack into r0 (param register)
 366         .endm
 367
 368         .macro  irq_save_user_regs
 369         sub     sp, sp, #S_FRAME_SIZE
 370         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 371         @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 372         add     r8, sp, #S_PC
 373         stmdb   r8, {sp, lr}^           @ Calling SP, LR
 374         str     lr, [r8, #0]            @ Save calling PC
 375         mrs     r6, spsr
 376         str     r6, [r8, #4]            @ Save CPSR
 377         str     r0, [r8, #8]            @ Save OLD_R0
 378         mov     r0, sp
 379         .endm
 380
 381         .macro  irq_restore_user_regs
 382         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 383         mov     r0, r0
 384         ldr     lr, [sp, #S_PC]                 @ Get PC
 385         add     sp, sp, #S_FRAME_SIZE
 386         subs    pc, lr, #4              @ return & move spsr_svc into cpsr
 387         .endm
 388
 389         .macro get_bad_stack
 390         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 391
 392         str     lr, [r13]       @ save caller lr in position 0 of saved stack
 393         mrs     lr, spsr        @ get the spsr
 394         str     lr, [r13, #4]   @ save spsr in position 1 of saved stack
 395         mov     r13, #MODE_SVC  @ prepare SVC-Mode
 396         @ msr   spsr_c, r13
 397         msr     spsr, r13       @ switch modes, make sure moves will execute
 398         mov     lr, pc          @ capture return pc
 399         movs    pc, lr          @ jump to next instruction & switch modes.
 400         .endm
 401
 402         .macro get_irq_stack                    @ setup IRQ stack
 403         ldr     sp, IRQ_STACK_START
 404         .endm
 405
 406         .macro get_fiq_stack                    @ setup FIQ stack
 407         ldr     sp, FIQ_STACK_START
 408         .endm
 409
 410 /*
 411  * exception handlers
 412  */
 413         .align  5
 414 undefined_instruction:
 415         get_bad_stack
 416         bad_save_user_regs
 417         bl      do_undefined_instruction
 418
 419         .align  5
 420 software_interrupt:
 421         get_bad_stack
 422         bad_save_user_regs
 423         bl      do_software_interrupt
 424
 425         .align  5
 426 prefetch_abort:
 427         get_bad_stack
 428         bad_save_user_regs
 429         bl      do_prefetch_abort
 430
 431         .align  5
 432 data_abort:
 433         get_bad_stack
 434         bad_save_user_regs
 435         bl      do_data_abort
 436
 437         .align  5
 438 not_used:
 439         get_bad_stack
 440         bad_save_user_regs
 441         bl      do_not_used
 442
 443 #ifdef CONFIG_USE_IRQ
 444
 445         .align  5
 446 irq:
 447         get_irq_stack
 448         irq_save_user_regs
 449         bl      do_irq
 450         irq_restore_user_regs
 451
 452         .align  5
 453 fiq:
 454         get_fiq_stack
 455         /* someone ought to write a more effiction fiq_save_user_regs */
 456         irq_save_user_regs
 457         bl      do_fiq
 458         irq_restore_user_regs
 459
 460 #else
 461
 462         .align  5
 463 irq:
 464         get_bad_stack
 465         bad_save_user_regs
 466         bl      do_irq
 467
 468         .align  5
 469 fiq:
 470         get_bad_stack
 471         bad_save_user_regs
 472         bl      do_fiq
 473
 474 #endif
 475
 476 # ifdef CONFIG_INTEGRATOR
 477
 478         /* Satisfied by general board level routine */
 479
 480 #else
 481
 482         .align  5
 483 .globl reset_cpu
 484 reset_cpu:
 485
 486         ldr     r1, rstctl1     /* get clkm1 reset ctl */
 487         mov     r3, #0x0
 488         strh    r3, [r1]        /* clear it */
 489         mov     r3, #0x8
 490         strh    r3, [r1]        /* force dsp+arm reset */
 491 _loop_forever:
 492         b       _loop_forever
 493
 494 rstctl1:
 495         .word   0xfffece10
 496
 497 #endif  /* #ifdef CONFIG_INTEGRATOR */