arch/arm/cpu/arm_intcm/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #include <asm-offsets.h>
  34 #include <config.h>
  35 #include <version.h>
  36
  37 /*
  38  *************************************************************************
  39  *
  40  * Jump vector table
  41  *
  42  *************************************************************************
  43  */
  44
  45 .globl _start
  46 _start:
  47         b       reset
  48         ldr     pc, _undefined_instruction
  49         ldr     pc, _software_interrupt
  50         ldr     pc, _prefetch_abort
  51         ldr     pc, _data_abort
  52         ldr     pc, _not_used
  53         ldr     pc, _irq
  54         ldr     pc, _fiq
  55
  56 _undefined_instruction:
  57         .word undefined_instruction
  58 _software_interrupt:
  59         .word software_interrupt
  60 _prefetch_abort:
  61         .word prefetch_abort
  62 _data_abort:
  63         .word data_abort
  64 _not_used:
  65         .word not_used
  66 _irq:
  67         .word irq
  68 _fiq:
  69         .word fiq
  70
  71         .balignl 16,0xdeadbeef
  72
  73 /*
  74  *************************************************************************
  75  *
  76  * Startup Code (reset vector)
  77  *
  78  * do important init only if we don't start from memory!
  79  * setup memory and board specific bits prior to relocation.
  80  * relocate armboot to ram
  81  * setup stack
  82  *
  83  *************************************************************************
  84  */
  85
  86 .globl _TEXT_BASE
  87 _TEXT_BASE:
  88 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  89         .word   CONFIG_SPL_TEXT_BASE
  90 #else
  91         .word   CONFIG_SYS_TEXT_BASE
  92 #endif
  93
  94 /*
  95  * These are defined in the board-specific linker script.
  96  * Subtracting _start from them lets the linker put their
  97  * relative position in the executable instead of leaving
  98  * them null.
  99  */
 100 .globl _bss_start_ofs
 101 _bss_start_ofs:
 102         .word __bss_start - _start
 103
 104 .globl _bss_end_ofs
 105 _bss_end_ofs:
 106         .word __bss_end - _start
 107
 108 .globl _end_ofs
 109 _end_ofs:
 110         .word _end - _start
 111
 112 #ifdef CONFIG_USE_IRQ
 113 /* IRQ stack memory (calculated at run-time) */
 114 .globl IRQ_STACK_START
 115 IRQ_STACK_START:
 116         .word   0x0badc0de
 117
 118 /* IRQ stack memory (calculated at run-time) */
 119 .globl FIQ_STACK_START
 120 FIQ_STACK_START:
 121         .word 0x0badc0de
 122 #endif
 123
 124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 125 .globl IRQ_STACK_START_IN
 126 IRQ_STACK_START_IN:
 127         .word   0x0badc0de
 128
 129 /*
 130  * the actual reset code
 131  */
 132
 133 reset:
 134         /*
 135          * set the cpu to SVC32 mode
 136          */
 137         mrs     r0,cpsr
 138         bic     r0,r0,#0x1f
 139         orr     r0,r0,#0xd3
 140         msr     cpsr,r0
 141
 142         /*
 143          * we do sys-critical inits only at reboot,
 144          * not when booting from ram!
 145          */
 146 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 147         bl      cpu_init_crit
 148 #endif
 149
 150         bl      _main
 151
 152 /*------------------------------------------------------------------------------*/
 153
 154 /*
 155  * void relocate_code (addr_sp, gd, addr_moni)
 156  *
 157  * This function relocates the monitor code.
 158  */
 159         .globl  relocate_code
 160 relocate_code:
 161         mov     r4, r0  /* save addr_sp */
 162         mov     r5, r1  /* save addr of gd */
 163         mov     r6, r2  /* save addr of destination */
 164
 165         adr     r0, _start
 166         subs    r9, r6, r0              /* r9 <- relocation offset */
 167         beq     relocate_done           /* skip relocation */
 168         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 169         ldr     r3, _bss_start_ofs
 170         add     r2, r0, r3              /* r2 <- source end address         */
 171
 172 copy_loop:
 173         ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
 174         stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
 175         cmp     r0, r2                  /* until source end address [r2]    */
 176         blo     copy_loop
 177
 178 #ifndef CONFIG_SPL_BUILD
 179         /*
 180          * fix .rel.dyn relocations
 181          */
 182         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 183         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 184         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 185         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 186         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 187         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 188         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 189 fixloop:
 190         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 191         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 192         ldr     r1, [r2, #4]
 193         and     r7, r1, #0xff
 194         cmp     r7, #23                 /* relative fixup? */
 195         beq     fixrel
 196         cmp     r7, #2                  /* absolute fixup? */
 197         beq     fixabs
 198         /* ignore unknown type of fixup */
 199         b       fixnext
 200 fixabs:
 201         /* absolute fix: set location to (offset) symbol value */
 202         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 203         add     r1, r10, r1             /* r1 <- address of symbol in table */
 204         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 205         add     r1, r1, r9              /* r1 <- relocated sym addr */
 206         b       fixnext
 207 fixrel:
 208         /* relative fix: increase location by offset */
 209         ldr     r1, [r0]
 210         add     r1, r1, r9
 211 fixnext:
 212         str     r1, [r0]
 213         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 214         cmp     r2, r3
 215         blo     fixloop
 216 #endif
 217
 218 relocate_done:
 219
 220         bx      lr
 221
 222 _rel_dyn_start_ofs:
 223         .word __rel_dyn_start - _start
 224 _rel_dyn_end_ofs:
 225         .word __rel_dyn_end - _start
 226 _dynsym_start_ofs:
 227         .word __dynsym_start - _start
 228
 229         .globl  c_runtime_cpu_setup
 230 c_runtime_cpu_setup:
 231
 232         mov     pc, lr
 233
 234 /*
 235  *************************************************************************
 236  *
 237  * CPU_init_critical registers
 238  *
 239  * setup important registers
 240  * setup memory timing
 241  *
 242  *************************************************************************
 243  */
 244
 245 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 246 cpu_init_crit:
 247         /*  arm_int_generic assumes the ARM boot monitor, or user software,
 248          * has initialized the platform
 249          */
 250         mov     pc, lr          /* back to my caller */
 251 #endif
 252 /*
 253  *************************************************************************
 254  *
 255  * Interrupt handling
 256  *
 257  *************************************************************************
 258  */
 259
 260 @
 261 @ IRQ stack frame.
 262 @
 263 #define S_FRAME_SIZE    72
 264
 265 #define S_OLD_R0        68
 266 #define S_PSR           64
 267 #define S_PC            60
 268 #define S_LR            56
 269 #define S_SP            52
 270
 271 #define S_IP            48
 272 #define S_FP            44
 273 #define S_R10           40
 274 #define S_R9            36
 275 #define S_R8            32
 276 #define S_R7            28
 277 #define S_R6            24
 278 #define S_R5            20
 279 #define S_R4            16
 280 #define S_R3            12
 281 #define S_R2            8
 282 #define S_R1            4
 283 #define S_R0            0
 284
 285 #define MODE_SVC 0x13
 286 #define I_BIT    0x80
 287
 288 /*
 289  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 290  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 291  */
 292
 293         .macro  bad_save_user_regs
 294         @ carve out a frame on current user stack
 295         sub     sp, sp, #S_FRAME_SIZE
 296         stmia   sp, {r0 - r12}  @ Save user registers (now in svc mode) r0-r12
 297
 298         ldr     r2, IRQ_STACK_START_IN
 299         @ get values for "aborted" pc and cpsr (into parm regs)
 300         ldmia   r2, {r2 - r3}
 301         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 302         add     r5, sp, #S_SP
 303         mov     r1, lr
 304         stmia   r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
 305         mov     r0, sp          @ save current stack into r0 (param register)
 306         .endm
 307
 308         .macro  irq_save_user_regs
 309         sub     sp, sp, #S_FRAME_SIZE
 310         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 311         @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 312         add     r8, sp, #S_PC
 313         stmdb   r8, {sp, lr}^           @ Calling SP, LR
 314         str     lr, [r8, #0]            @ Save calling PC
 315         mrs     r6, spsr
 316         str     r6, [r8, #4]            @ Save CPSR
 317         str     r0, [r8, #8]            @ Save OLD_R0
 318         mov     r0, sp
 319         .endm
 320
 321         .macro  irq_restore_user_regs
 322         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 323         mov     r0, r0
 324         ldr     lr, [sp, #S_PC]                 @ Get PC
 325         add     sp, sp, #S_FRAME_SIZE
 326         subs    pc, lr, #4              @ return & move spsr_svc into cpsr
 327         .endm
 328
 329         .macro get_bad_stack
 330         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 331
 332         str     lr, [r13]       @ save caller lr in position 0 of saved stack
 333         mrs     lr, spsr        @ get the spsr
 334         str     lr, [r13, #4]   @ save spsr in position 1 of saved stack
 335         mov     r13, #MODE_SVC  @ prepare SVC-Mode
 336         @ msr   spsr_c, r13
 337         msr     spsr, r13       @ switch modes, make sure moves will execute
 338         mov     lr, pc          @ capture return pc
 339         movs    pc, lr          @ jump to next instruction & switch modes.
 340         .endm
 341
 342         .macro get_irq_stack                    @ setup IRQ stack
 343         ldr     sp, IRQ_STACK_START
 344         .endm
 345
 346         .macro get_fiq_stack                    @ setup FIQ stack
 347         ldr     sp, FIQ_STACK_START
 348         .endm
 349
 350 /*
 351  * exception handlers
 352  */
 353         .align  5
 354 .globl undefined_instruction
 355 undefined_instruction:
 356         get_bad_stack
 357         bad_save_user_regs
 358         bl      do_undefined_instruction
 359
 360         .align  5
 361 .globl software_interrupt
 362 software_interrupt:
 363         get_bad_stack
 364         bad_save_user_regs
 365         bl      do_software_interrupt
 366
 367         .align  5
 368 .globl prefetch_abort
 369 prefetch_abort:
 370         get_bad_stack
 371         bad_save_user_regs
 372         bl      do_prefetch_abort
 373
 374         .align  5
 375 .globl data_abort
 376 data_abort:
 377         get_bad_stack
 378         bad_save_user_regs
 379         bl      do_data_abort
 380
 381         .align  5
 382 .globl not_used
 383 not_used:
 384         get_bad_stack
 385         bad_save_user_regs
 386         bl      do_not_used
 387
 388 #ifdef CONFIG_USE_IRQ
 389         .align  5
 390 .globl irq
 391 irq:
 392         get_irq_stack
 393         irq_save_user_regs
 394         bl      do_irq
 395         irq_restore_user_regs
 396
 397         .align  5
 398 .globl fiq
 399 fiq:
 400         get_fiq_stack
 401         /* someone ought to write a more effiction fiq_save_user_regs */
 402         irq_save_user_regs
 403         bl      do_fiq
 404         irq_restore_user_regs
 405
 406 #else
 407
 408         .align  5
 409 .globl irq
 410 irq:
 411         get_bad_stack
 412         bad_save_user_regs
 413         bl      do_irq
 414
 415         .align  5
 416 .globl fiq
 417 fiq:
 418         get_bad_stack
 419         bad_save_user_regs
 420         bl      do_fiq
 421
 422 #endif