arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/common_def.h>
  27 #include <asm/io.h>
  28 #include <asm/omap_common.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  33 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  34 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  35
  36 /* UART Defines */
  37 #ifdef CONFIG_SPL_BUILD
  38 #define UART_RESET              (0x1 << 1)
  39 #define UART_CLK_RUNNING_MASK   0x1
  40 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
  41 #endif
  42
  43 /*
  44  * early system init of muxing and clocks.
  45  */
  46 void s_init(void)
  47 {
  48         /* WDT1 is already running when the bootloader gets control
  49          * Disable it to avoid "random" resets
  50          */
  51         writel(0xAAAA, &wdtimer->wdtwspr);
  52         while (readl(&wdtimer->wdtwwps) != 0x0)
  53                 ;
  54         writel(0x5555, &wdtimer->wdtwspr);
  55         while (readl(&wdtimer->wdtwwps) != 0x0)
  56                 ;
  57
  58 #ifdef CONFIG_SPL_BUILD
  59         /* Setup the PLLs and the clocks for the peripherals */
  60         pll_init();
  61
  62         /* UART softreset */
  63         u32 regVal;
  64
  65         enable_uart0_pin_mux();
  66
  67         regVal = readl(&uart_base->uartsyscfg);
  68         regVal |= UART_RESET;
  69         writel(regVal, &uart_base->uartsyscfg);
  70         while ((readl(&uart_base->uartsyssts) &
  71                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  72                 ;
  73
  74         /* Disable smart idle */
  75         regVal = readl(&uart_base->uartsyscfg);
  76         regVal |= UART_SMART_IDLE_EN;
  77         writel(regVal, &uart_base->uartsyscfg);
  78
  79         /* Initialize the Timer */
  80         init_timer();
  81
  82         preloader_console_init();
  83
  84         config_ddr();
  85 #endif
  86
  87         /* Enable MMC0 */
  88         enable_mmc0_pin_mux();
  89 }
  90
  91 /* Initialize timer */
  92 void init_timer(void)
  93 {
  94         /* Reset the Timer */
  95         writel(0x2, (&timer_base->tscir));
  96
  97         /* Wait until the reset is done */
  98         while (readl(&timer_base->tiocp_cfg) & 1)
  99                 ;
 100
 101         /* Start the Timer */
 102         writel(0x1, (&timer_base->tclr));
 103 }
 104
 105 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 106 int board_mmc_init(bd_t *bis)
 107 {
 108         return omap_mmc_init(0);
 109 }
 110 #endif
 111
 112 void setup_clocks_for_console(void)
 113 {
 114         /* Not yet implemented */
 115         return;
 116 }