4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
29 #include <asm/errno.h>
30 #include <linux/compiler.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/musb.h>
34 #include <asm/omap_musb.h>
35 #include <asm/davinci_rtc.h>
37 DECLARE_GLOBAL_DATA_PTR
;
39 static const struct gpio_bank gpio_bank_am33xx
[] = {
40 { (void *)AM33XX_GPIO0_BASE
, METHOD_GPIO_24XX
},
41 { (void *)AM33XX_GPIO1_BASE
, METHOD_GPIO_24XX
},
42 { (void *)AM33XX_GPIO2_BASE
, METHOD_GPIO_24XX
},
43 { (void *)AM33XX_GPIO3_BASE
, METHOD_GPIO_24XX
},
45 { (void *)AM33XX_GPIO4_BASE
, METHOD_GPIO_24XX
},
46 { (void *)AM33XX_GPIO5_BASE
, METHOD_GPIO_24XX
},
50 const struct gpio_bank
*const omap_gpio_bank
= gpio_bank_am33xx
;
52 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
53 int cpu_mmc_init(bd_t
*bis
)
57 ret
= omap_mmc_init(0, 0, 0, -1, -1);
61 return omap_mmc_init(1, 0, 0, -1, -1);
65 /* AM33XX has two MUSB controllers which can be host or gadget */
66 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
67 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
68 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
70 /* USB 2.0 PHY Control */
71 #define CM_PHY_PWRDN (1 << 0)
72 #define CM_PHY_OTG_PWRDN (1 << 1)
73 #define OTGVDET_EN (1 << 19)
74 #define OTGSESSENDEN (1 << 20)
76 static void am33xx_usb_set_phy_power(u8 on
, u32
*reg_addr
)
79 clrsetbits_le32(reg_addr
, CM_PHY_PWRDN
| CM_PHY_OTG_PWRDN
,
80 OTGVDET_EN
| OTGSESSENDEN
);
82 clrsetbits_le32(reg_addr
, 0, CM_PHY_PWRDN
| CM_PHY_OTG_PWRDN
);
86 static struct musb_hdrc_config musb_config
= {
93 #ifdef CONFIG_AM335X_USB0
94 static void am33xx_otg0_set_phy_power(u8 on
)
96 am33xx_usb_set_phy_power(on
, &cdev
->usb_ctrl0
);
99 struct omap_musb_board_data otg0_board_data
= {
100 .set_phy_power
= am33xx_otg0_set_phy_power
,
103 static struct musb_hdrc_platform_data otg0_plat
= {
104 .mode
= CONFIG_AM335X_USB0_MODE
,
105 .config
= &musb_config
,
107 .platform_ops
= &musb_dsps_ops
,
108 .board_data
= &otg0_board_data
,
112 #ifdef CONFIG_AM335X_USB1
113 static void am33xx_otg1_set_phy_power(u8 on
)
115 am33xx_usb_set_phy_power(on
, &cdev
->usb_ctrl1
);
118 struct omap_musb_board_data otg1_board_data
= {
119 .set_phy_power
= am33xx_otg1_set_phy_power
,
122 static struct musb_hdrc_platform_data otg1_plat
= {
123 .mode
= CONFIG_AM335X_USB1_MODE
,
124 .config
= &musb_config
,
126 .platform_ops
= &musb_dsps_ops
,
127 .board_data
= &otg1_board_data
,
132 int arch_misc_init(void)
134 #ifdef CONFIG_AM335X_USB0
135 musb_register(&otg0_plat
, &otg0_board_data
,
136 (void *)USB0_OTG_BASE
);
138 #ifdef CONFIG_AM335X_USB1
139 musb_register(&otg1_plat
, &otg1_board_data
,
140 (void *)USB1_OTG_BASE
);
145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
147 * This function is the place to do per-board things such as ramp up the
148 * MPU clock frequency.
150 __weak
void am33xx_spl_board_init(void)
152 do_setup_dpll(&dpll_core_regs
, &dpll_core_opp100
);
153 do_setup_dpll(&dpll_mpu_regs
, &dpll_mpu_opp100
);
156 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
157 static void rtc32k_enable(void)
159 struct davinci_rtc
*rtc
= (struct davinci_rtc
*)RTC_BASE
;
162 * Unlock the RTC's registers. For more details please see the
163 * RTC_SS section of the TRM. In order to unlock we need to
164 * write these specific values (keys) in this order.
166 writel(RTC_KICK0R_WE
, &rtc
->kick0r
);
167 writel(RTC_KICK1R_WE
, &rtc
->kick1r
);
169 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
170 writel((1 << 3) | (1 << 6), &rtc
->osc
);
174 static void uart_soft_reset(void)
176 struct uart_sys
*uart_base
= (struct uart_sys
*)DEFAULT_UART_BASE
;
179 regval
= readl(&uart_base
->uartsyscfg
);
180 regval
|= UART_RESET
;
181 writel(regval
, &uart_base
->uartsyscfg
);
182 while ((readl(&uart_base
->uartsyssts
) &
183 UART_CLK_RUNNING_MASK
) != UART_CLK_RUNNING_MASK
)
186 /* Disable smart idle */
187 regval
= readl(&uart_base
->uartsyscfg
);
188 regval
|= UART_SMART_IDLE_EN
;
189 writel(regval
, &uart_base
->uartsyscfg
);
192 static void watchdog_disable(void)
194 struct wd_timer
*wdtimer
= (struct wd_timer
*)WDT_BASE
;
196 writel(0xAAAA, &wdtimer
->wdtwspr
);
197 while (readl(&wdtimer
->wdtwwps
) != 0x0)
199 writel(0x5555, &wdtimer
->wdtwspr
);
200 while (readl(&wdtimer
->wdtwwps
) != 0x0)
207 * The ROM will only have set up sufficient pinmux to allow for the
208 * first 4KiB NOR to be read, we must finish doing what we know of
209 * the NOR mux in this space in order to continue.
211 #ifdef CONFIG_NOR_BOOT
212 enable_norboot_pin_mux();
215 * Save the boot parameters passed from romcode.
216 * We cannot delay the saving further than this,
217 * to prevent overwrites.
219 #ifdef CONFIG_SPL_BUILD
220 save_omap_boot_params();
225 setup_clocks_for_console();
227 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
228 gd
->baudrate
= CONFIG_BAUDRATE
;
230 gd
->have_console
= 1;
231 #elif defined(CONFIG_SPL_BUILD)
233 preloader_console_init();
237 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
238 /* Enable RTC32K clock */
245 #ifndef CONFIG_SYS_DCACHE_OFF
246 void enable_caches(void)
248 /* Enable D-cache. I-cache is already enabled in start.S */
251 #endif /* !CONFIG_SYS_DCACHE_OFF */