arch/arm/cpu/armv7/am33xx/clock.c

   1 /*
   2  * clock.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27
  28 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  29 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  30
  31 #define PLL_BYPASS_MODE         0x4
  32 #define ST_MN_BYPASS            0x00000100
  33 #define ST_DPLL_CLK             0x00000001
  34 #define CLK_SEL_MASK            0x7ffff
  35 #define CLK_DIV_MASK            0x1f
  36 #define CLK_DIV2_MASK           0x7f
  37 #define CLK_SEL_SHIFT           0x8
  38 #define CLK_MODE_SEL            0x7
  39 #define CLK_MODE_MASK           0xfffffff8
  40 #define CLK_DIV_SEL             0xFFFFFFE0
  41
  42
  43 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  44 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  45 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  46
  47 static void enable_interface_clocks(void)
  48 {
  49         /* Enable all the Interconnect Modules */
  50         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  51         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  52                 ;
  53
  54         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  55         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  56                 ;
  57
  58         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  59         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  60                 ;
  61
  62         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  63         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  64                 ;
  65
  66         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  67         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  68                 ;
  69
  70         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  71         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  72                 ;
  73 }
  74
  75 /*
  76  * Force power domain wake up transition
  77  * Ensure that the corresponding interface clock is active before
  78  * using the peripheral
  79  */
  80 static void power_domain_wkup_transition(void)
  81 {
  82         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  83         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  84         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  85         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  86         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  87 }
  88
  89 /*
  90  * Enable the peripheral clock for required peripherals
  91  */
  92 static void enable_per_clocks(void)
  93 {
  94         /* Enable the control module though RBL would have done it*/
  95         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
  96         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
  97                 ;
  98
  99         /* Enable the module clock */
 100         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 101         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 102                 ;
 103
 104         /* Select the Master osc 24 MHZ as Timer2 clock source */
 105         writel(0x1, &cmdpll->clktimer2clk);
 106
 107         /* UART0 */
 108         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 109         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 110                 ;
 111
 112         /* MMC0*/
 113         writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 114         while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 115                 ;
 116 }
 117
 118 static void mpu_pll_config(void)
 119 {
 120         u32 clkmode, clksel, div_m2;
 121
 122         clkmode = readl(&cmwkup->clkmoddpllmpu);
 123         clksel = readl(&cmwkup->clkseldpllmpu);
 124         div_m2 = readl(&cmwkup->divm2dpllmpu);
 125
 126         /* Set the PLL to bypass Mode */
 127         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 128         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 129                 ;
 130
 131         clksel = clksel & (~CLK_SEL_MASK);
 132         clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 133         writel(clksel, &cmwkup->clkseldpllmpu);
 134
 135         div_m2 = div_m2 & ~CLK_DIV_MASK;
 136         div_m2 = div_m2 | MPUPLL_M2;
 137         writel(div_m2, &cmwkup->divm2dpllmpu);
 138
 139         clkmode = clkmode | CLK_MODE_SEL;
 140         writel(clkmode, &cmwkup->clkmoddpllmpu);
 141
 142         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 143                 ;
 144 }
 145
 146 static void core_pll_config(void)
 147 {
 148         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 149
 150         clkmode = readl(&cmwkup->clkmoddpllcore);
 151         clksel = readl(&cmwkup->clkseldpllcore);
 152         div_m4 = readl(&cmwkup->divm4dpllcore);
 153         div_m5 = readl(&cmwkup->divm5dpllcore);
 154         div_m6 = readl(&cmwkup->divm6dpllcore);
 155
 156         /* Set the PLL to bypass Mode */
 157         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 158
 159         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 160                 ;
 161
 162         clksel = clksel & (~CLK_SEL_MASK);
 163         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 164         writel(clksel, &cmwkup->clkseldpllcore);
 165
 166         div_m4 = div_m4 & ~CLK_DIV_MASK;
 167         div_m4 = div_m4 | COREPLL_M4;
 168         writel(div_m4, &cmwkup->divm4dpllcore);
 169
 170         div_m5 = div_m5 & ~CLK_DIV_MASK;
 171         div_m5 = div_m5 | COREPLL_M5;
 172         writel(div_m5, &cmwkup->divm5dpllcore);
 173
 174         div_m6 = div_m6 & ~CLK_DIV_MASK;
 175         div_m6 = div_m6 | COREPLL_M6;
 176         writel(div_m6, &cmwkup->divm6dpllcore);
 177
 178         clkmode = clkmode | CLK_MODE_SEL;
 179         writel(clkmode, &cmwkup->clkmoddpllcore);
 180
 181         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 182                 ;
 183 }
 184
 185 static void per_pll_config(void)
 186 {
 187         u32 clkmode, clksel, div_m2;
 188
 189         clkmode = readl(&cmwkup->clkmoddpllper);
 190         clksel = readl(&cmwkup->clkseldpllper);
 191         div_m2 = readl(&cmwkup->divm2dpllper);
 192
 193         /* Set the PLL to bypass Mode */
 194         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 195
 196         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 197                 ;
 198
 199         clksel = clksel & (~CLK_SEL_MASK);
 200         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 201         writel(clksel, &cmwkup->clkseldpllper);
 202
 203         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 204         div_m2 = div_m2 | PERPLL_M2;
 205         writel(div_m2, &cmwkup->divm2dpllper);
 206
 207         clkmode = clkmode | CLK_MODE_SEL;
 208         writel(clkmode, &cmwkup->clkmoddpllper);
 209
 210         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 211                 ;
 212 }
 213
 214 static void ddr_pll_config(void)
 215 {
 216         u32 clkmode, clksel, div_m2;
 217
 218         clkmode = readl(&cmwkup->clkmoddpllddr);
 219         clksel = readl(&cmwkup->clkseldpllddr);
 220         div_m2 = readl(&cmwkup->divm2dpllddr);
 221
 222         /* Set the PLL to bypass Mode */
 223         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 224         writel(clkmode, &cmwkup->clkmoddpllddr);
 225
 226         /* Wait till bypass mode is enabled */
 227         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 228                                 != ST_MN_BYPASS)
 229                 ;
 230
 231         clksel = clksel & (~CLK_SEL_MASK);
 232         clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
 233         writel(clksel, &cmwkup->clkseldpllddr);
 234
 235         div_m2 = div_m2 & CLK_DIV_SEL;
 236         div_m2 = div_m2 | DDRPLL_M2;
 237         writel(div_m2, &cmwkup->divm2dpllddr);
 238
 239         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 240         writel(clkmode, &cmwkup->clkmoddpllddr);
 241
 242         /* Wait till dpll is locked */
 243         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 244                 ;
 245 }
 246
 247 void enable_emif_clocks(void)
 248 {
 249         /* Enable the  EMIF_FW Functional clock */
 250         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 251         /* Enable EMIF0 Clock */
 252         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 253         /* Poll for emif_gclk  & L3_G clock  are active */
 254         while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
 255                         PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
 256                         PRCM_L3_GCLK_ACTIVITY))
 257                 ;
 258         /* Poll if module is functional */
 259         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 260                 ;
 261 }
 262
 263 /*
 264  * Configure the PLL/PRCM for necessary peripherals
 265  */
 266 void pll_init()
 267 {
 268         mpu_pll_config();
 269         core_pll_config();
 270         per_pll_config();
 271         ddr_pll_config();
 272
 273         /* Enable the required interconnect clocks */
 274         enable_interface_clocks();
 275
 276         /* Power domain wake up transition */
 277         power_domain_wkup_transition();
 278
 279         /* Enable the required peripherals */
 280         enable_per_clocks();
 281 }