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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/arm/cpu/armv7/am33xx/ddr.c
2 * DDR Configuration for AM33xx devices.
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/ddr_defs.h>
11 #include <asm/arch/sys_proto.h>
16 * Base address for EMIF instances
18 static struct emif_reg_struct
*emif_reg
[2] = {
19 (struct emif_reg_struct
*)EMIF4_0_CFG_BASE
,
20 (struct emif_reg_struct
*)EMIF4_1_CFG_BASE
};
23 * Base addresses for DDR PHY cmd/data regs
25 static struct ddr_cmd_regs
*ddr_cmd_reg
[2] = {
26 (struct ddr_cmd_regs
*)DDR_PHY_CMD_ADDR
,
27 (struct ddr_cmd_regs
*)DDR_PHY_CMD_ADDR2
};
29 static struct ddr_data_regs
*ddr_data_reg
[2] = {
30 (struct ddr_data_regs
*)DDR_PHY_DATA_ADDR
,
31 (struct ddr_data_regs
*)DDR_PHY_DATA_ADDR2
};
34 * Base address for ddr io control instances
36 static struct ddr_cmdtctrl
*ioctrl_reg
= {
37 (struct ddr_cmdtctrl
*)DDR_CONTROL_BASE_ADDR
};
42 void config_sdram(const struct emif_regs
*regs
, int nr
)
44 if (regs
->zq_config
) {
46 * A value of 0x2800 for the REF CTRL will give us
47 * about 570us for a delay, which will be long enough
48 * to configure things.
50 writel(0x2800, &emif_reg
[nr
]->emif_sdram_ref_ctrl
);
51 writel(regs
->zq_config
, &emif_reg
[nr
]->emif_zq_config
);
52 writel(regs
->sdram_config
, &cstat
->secure_emif_sdram_config
);
53 writel(regs
->sdram_config
, &emif_reg
[nr
]->emif_sdram_config
);
54 writel(regs
->ref_ctrl
, &emif_reg
[nr
]->emif_sdram_ref_ctrl
);
55 writel(regs
->ref_ctrl
, &emif_reg
[nr
]->emif_sdram_ref_ctrl_shdw
);
57 writel(regs
->ref_ctrl
, &emif_reg
[nr
]->emif_sdram_ref_ctrl
);
58 writel(regs
->ref_ctrl
, &emif_reg
[nr
]->emif_sdram_ref_ctrl_shdw
);
59 writel(regs
->sdram_config
, &emif_reg
[nr
]->emif_sdram_config
);
65 void set_sdram_timings(const struct emif_regs
*regs
, int nr
)
67 writel(regs
->sdram_tim1
, &emif_reg
[nr
]->emif_sdram_tim_1
);
68 writel(regs
->sdram_tim1
, &emif_reg
[nr
]->emif_sdram_tim_1_shdw
);
69 writel(regs
->sdram_tim2
, &emif_reg
[nr
]->emif_sdram_tim_2
);
70 writel(regs
->sdram_tim2
, &emif_reg
[nr
]->emif_sdram_tim_2_shdw
);
71 writel(regs
->sdram_tim3
, &emif_reg
[nr
]->emif_sdram_tim_3
);
72 writel(regs
->sdram_tim3
, &emif_reg
[nr
]->emif_sdram_tim_3_shdw
);
78 void config_ddr_phy(const struct emif_regs
*regs
, int nr
)
80 writel(regs
->emif_ddr_phy_ctlr_1
,
81 &emif_reg
[nr
]->emif_ddr_phy_ctrl_1
);
82 writel(regs
->emif_ddr_phy_ctlr_1
,
83 &emif_reg
[nr
]->emif_ddr_phy_ctrl_1_shdw
);
87 * Configure DDR CMD control registers
89 void config_cmd_ctrl(const struct cmd_control
*cmd
, int nr
)
91 writel(cmd
->cmd0csratio
, &ddr_cmd_reg
[nr
]->cm0csratio
);
92 writel(cmd
->cmd0dldiff
, &ddr_cmd_reg
[nr
]->cm0dldiff
);
93 writel(cmd
->cmd0iclkout
, &ddr_cmd_reg
[nr
]->cm0iclkout
);
95 writel(cmd
->cmd1csratio
, &ddr_cmd_reg
[nr
]->cm1csratio
);
96 writel(cmd
->cmd1dldiff
, &ddr_cmd_reg
[nr
]->cm1dldiff
);
97 writel(cmd
->cmd1iclkout
, &ddr_cmd_reg
[nr
]->cm1iclkout
);
99 writel(cmd
->cmd2csratio
, &ddr_cmd_reg
[nr
]->cm2csratio
);
100 writel(cmd
->cmd2dldiff
, &ddr_cmd_reg
[nr
]->cm2dldiff
);
101 writel(cmd
->cmd2iclkout
, &ddr_cmd_reg
[nr
]->cm2iclkout
);
105 * Configure DDR DATA registers
107 void config_ddr_data(const struct ddr_data
*data
, int nr
)
111 for (i
= 0; i
< DDR_DATA_REGS_NR
; i
++) {
112 writel(data
->datardsratio0
,
113 &(ddr_data_reg
[nr
]+i
)->dt0rdsratio0
);
114 writel(data
->datawdsratio0
,
115 &(ddr_data_reg
[nr
]+i
)->dt0wdsratio0
);
116 writel(data
->datawiratio0
,
117 &(ddr_data_reg
[nr
]+i
)->dt0wiratio0
);
118 writel(data
->datagiratio0
,
119 &(ddr_data_reg
[nr
]+i
)->dt0giratio0
);
120 writel(data
->datafwsratio0
,
121 &(ddr_data_reg
[nr
]+i
)->dt0fwsratio0
);
122 writel(data
->datawrsratio0
,
123 &(ddr_data_reg
[nr
]+i
)->dt0wrsratio0
);
124 writel(data
->datauserank0delay
,
125 &(ddr_data_reg
[nr
]+i
)->dt0rdelays0
);
126 writel(data
->datadldiff0
,
127 &(ddr_data_reg
[nr
]+i
)->dt0dldiff0
);
131 void config_io_ctrl(unsigned long val
)
133 writel(val
, &ioctrl_reg
->cm0ioctl
);
134 writel(val
, &ioctrl_reg
->cm1ioctl
);
135 writel(val
, &ioctrl_reg
->cm2ioctl
);
136 writel(val
, &ioctrl_reg
->dt0ioctl
);
137 writel(val
, &ioctrl_reg
->dt1ioctl
);