4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR
;
30 struct ddr_regs
*ddrregs
= (struct ddr_regs
*)DDR_PHY_BASE_ADDR
;
31 struct vtp_reg
*vtpreg
= (struct vtp_reg
*)VTP0_CTRL_ADDR
;
32 struct ddr_ctrl
*ddrctrl
= (struct ddr_ctrl
*)DDR_CTRL_ADDR
;
36 /* dram_init must store complete ramsize in gd->ram_size */
37 gd
->ram_size
= get_ram_size(
38 (void *)CONFIG_SYS_SDRAM_BASE
,
39 CONFIG_MAX_RAM_BANK_SIZE
);
43 void dram_init_banksize(void)
45 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
46 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
;
50 #ifdef CONFIG_SPL_BUILD
51 static const struct ddr_data ddr2_data
= {
52 .datardsratio0
= ((DDR2_RD_DQS
<<30)|(DDR2_RD_DQS
<<20)
53 |(DDR2_RD_DQS
<<10)|(DDR2_RD_DQS
<<0)),
54 .datardsratio1
= DDR2_RD_DQS
>>2,
55 .datawdsratio0
= ((DDR2_WR_DQS
<<30)|(DDR2_WR_DQS
<<20)
56 |(DDR2_WR_DQS
<<10)|(DDR2_WR_DQS
<<0)),
57 .datawdsratio1
= DDR2_WR_DQS
>>2,
58 .datawiratio0
= ((DDR2_PHY_WRLVL
<<30)|(DDR2_PHY_WRLVL
<<20)
59 |(DDR2_PHY_WRLVL
<<10)|(DDR2_PHY_WRLVL
<<0)),
60 .datawiratio1
= DDR2_PHY_WRLVL
>>2,
61 .datagiratio0
= ((DDR2_PHY_GATELVL
<<30)|(DDR2_PHY_GATELVL
<<20)
62 |(DDR2_PHY_GATELVL
<<10)|(DDR2_PHY_GATELVL
<<0)),
63 .datagiratio1
= DDR2_PHY_GATELVL
>>2,
64 .datafwsratio0
= ((DDR2_PHY_FIFO_WE
<<30)|(DDR2_PHY_FIFO_WE
<<20)
65 |(DDR2_PHY_FIFO_WE
<<10)|(DDR2_PHY_FIFO_WE
<<0)),
66 .datafwsratio1
= DDR2_PHY_FIFO_WE
>>2,
67 .datawrsratio0
= ((DDR2_PHY_WR_DATA
<<30)|(DDR2_PHY_WR_DATA
<<20)
68 |(DDR2_PHY_WR_DATA
<<10)|(DDR2_PHY_WR_DATA
<<0)),
69 .datawrsratio1
= DDR2_PHY_WR_DATA
>>2,
70 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
73 static const struct cmd_control ddr2_cmd_ctrl_data
= {
74 .cmd0csratio
= DDR2_RATIO
,
75 .cmd0csforce
= CMD_FORCE
,
76 .cmd0csdelay
= CMD_DELAY
,
77 .cmd0dldiff
= DDR2_DLL_LOCK_DIFF
,
78 .cmd0iclkout
= DDR2_INVERT_CLKOUT
,
80 .cmd1csratio
= DDR2_RATIO
,
81 .cmd1csforce
= CMD_FORCE
,
82 .cmd1csdelay
= CMD_DELAY
,
83 .cmd1dldiff
= DDR2_DLL_LOCK_DIFF
,
84 .cmd1iclkout
= DDR2_INVERT_CLKOUT
,
86 .cmd2csratio
= DDR2_RATIO
,
87 .cmd2csforce
= CMD_FORCE
,
88 .cmd2csdelay
= CMD_DELAY
,
89 .cmd2dldiff
= DDR2_DLL_LOCK_DIFF
,
90 .cmd2iclkout
= DDR2_INVERT_CLKOUT
,
93 static void config_vtp(void)
95 writel(readl(&vtpreg
->vtp0ctrlreg
) | VTP_CTRL_ENABLE
,
96 &vtpreg
->vtp0ctrlreg
);
97 writel(readl(&vtpreg
->vtp0ctrlreg
) & (~VTP_CTRL_START_EN
),
98 &vtpreg
->vtp0ctrlreg
);
99 writel(readl(&vtpreg
->vtp0ctrlreg
) | VTP_CTRL_START_EN
,
100 &vtpreg
->vtp0ctrlreg
);
103 while ((readl(&vtpreg
->vtp0ctrlreg
) & VTP_CTRL_READY
) !=
108 static void config_emif_ddr2(void)
110 struct sdram_config cfg
;
111 struct sdram_timing tmg
;
112 struct ddr_phy_control phyc
;
114 /* Program EMIF0 CFG Registers */
115 phyc
.reg
= DDR2_EMIF_READ_LATENCY
;
116 phyc
.reg_sh
= DDR2_EMIF_READ_LATENCY
;
117 phyc
.reg2
= DDR2_EMIF_READ_LATENCY
;
119 tmg
.time1
= DDR2_EMIF_TIM1
;
120 tmg
.time1_sh
= DDR2_EMIF_TIM1
;
121 tmg
.time2
= DDR2_EMIF_TIM2
;
122 tmg
.time2_sh
= DDR2_EMIF_TIM2
;
123 tmg
.time3
= DDR2_EMIF_TIM3
;
124 tmg
.time3_sh
= DDR2_EMIF_TIM3
;
126 cfg
.sdrcr
= DDR2_EMIF_SDCFG
;
127 cfg
.sdrcr2
= DDR2_EMIF_SDCFG
;
128 cfg
.refresh
= DDR2_EMIF_SDREF
;
129 cfg
.refresh_sh
= DDR2_EMIF_SDREF
;
131 /* Program EMIF instance */
132 config_ddr_phy(&phyc
);
133 set_sdram_timings(&tmg
);
137 void config_ddr(short ddr_type
)
139 struct ddr_ioctrl ioctrl
;
141 enable_emif_clocks();
143 if (ddr_type
== EMIF_REG_SDRAM_TYPE_DDR2
) {
147 config_cmd_ctrl(&ddr2_cmd_ctrl_data
);
149 config_ddr_data(0, &ddr2_data
);
150 config_ddr_data(1, &ddr2_data
);
152 writel(DDR2_PHY_RANK0_DELAY
, &ddrregs
->dt0rdelays0
);
153 writel(DDR2_PHY_RANK0_DELAY
, &ddrregs
->dt1rdelays0
);
155 ioctrl
.cmd1ctl
= DDR2_IOCTRL_VALUE
;
156 ioctrl
.cmd2ctl
= DDR2_IOCTRL_VALUE
;
157 ioctrl
.cmd3ctl
= DDR2_IOCTRL_VALUE
;
158 ioctrl
.data1ctl
= DDR2_IOCTRL_VALUE
;
159 ioctrl
.data2ctl
= DDR2_IOCTRL_VALUE
;
161 config_io_ctrl(&ioctrl
);
163 /* Set CKE to be controlled by EMIF/DDR PHY */
164 writel(DDR_CKE_CTRL_NORMAL
, &ddrctrl
->ddrckectrl
);