arch/arm/cpu/armv7/am33xx/emif4.c

   1 /*
   2  * emif4.c
   3  *
   4  * AM33XX emif4 configuration file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/ddr_defs.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int dram_init(void)
  31 {
  32         /* dram_init must store complete ramsize in gd->ram_size */
  33         gd->ram_size = get_ram_size(
  34                         (void *)CONFIG_SYS_SDRAM_BASE,
  35                         CONFIG_MAX_RAM_BANK_SIZE);
  36         return 0;
  37 }
  38
  39 void dram_init_banksize(void)
  40 {
  41         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  42         gd->bd->bi_dram[0].size = gd->ram_size;
  43 }
  44
  45
  46 #ifdef CONFIG_SPL_BUILD
  47 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
  48                                 (struct dmm_lisa_map_regs *)DMM_BASE;
  49 static struct vtp_reg *vtpreg[2] = {
  50                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  51                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  52 #ifdef CONFIG_AM33XX
  53 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  54 #endif
  55
  56 void config_dmm(const struct dmm_lisa_map_regs *regs)
  57 {
  58         enable_dmm_clocks();
  59
  60         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  61         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  62         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  63         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  64
  65         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  66         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  67         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  68         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  69 }
  70
  71 static void config_vtp(int nr)
  72 {
  73         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  74                         &vtpreg[nr]->vtp0ctrlreg);
  75         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  76                         &vtpreg[nr]->vtp0ctrlreg);
  77         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  78                         &vtpreg[nr]->vtp0ctrlreg);
  79
  80         /* Poll for READY */
  81         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  82                         VTP_CTRL_READY)
  83                 ;
  84 }
  85
  86 void config_ddr(unsigned int pll, unsigned int ioctrl,
  87                 const struct ddr_data *data, const struct cmd_control *ctrl,
  88                 const struct emif_regs *regs, int nr)
  89 {
  90         enable_emif_clocks();
  91         ddr_pll_config(pll);
  92         config_vtp(nr);
  93         config_cmd_ctrl(ctrl, nr);
  94
  95         config_ddr_data(data, nr);
  96 #ifdef CONFIG_AM33XX
  97         config_io_ctrl(ioctrl);
  98
  99         /* Set CKE to be controlled by EMIF/DDR PHY */
 100         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 101 #endif
 102
 103         /* Program EMIF instance */
 104         config_ddr_phy(regs, nr);
 105         set_sdram_timings(regs, nr);
 106         config_sdram(regs, nr);
 107 }
 108 #endif