arch/arm/cpu/armv7/am33xx/mem.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Mansoor Ahamed <mansoor.ahamed@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Manikandan Pillai <mani.pillai@ti.com>
  10  *     Richard Woodruff <r-woodruff2@ti.com>
  11  *     Syed Mohammed Khasim <khasim@ti.com>
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/cpu.h>
  32 #include <asm/arch/mem.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <command.h>
  35
  36 struct gpmc *gpmc_cfg;
  37
  38 #if defined(CONFIG_CMD_NAND)
  39 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  40         M_NAND_GPMC_CONFIG1,
  41         M_NAND_GPMC_CONFIG2,
  42         M_NAND_GPMC_CONFIG3,
  43         M_NAND_GPMC_CONFIG4,
  44         M_NAND_GPMC_CONFIG5,
  45         M_NAND_GPMC_CONFIG6, 0
  46 };
  47 #endif
  48
  49
  50 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  51                         u32 size)
  52 {
  53         writel(0, &cs->config7);
  54         sdelay(1000);
  55         /* Delay for settling */
  56         writel(gpmc_config[0], &cs->config1);
  57         writel(gpmc_config[1], &cs->config2);
  58         writel(gpmc_config[2], &cs->config3);
  59         writel(gpmc_config[3], &cs->config4);
  60         writel(gpmc_config[4], &cs->config5);
  61         writel(gpmc_config[5], &cs->config6);
  62         /* Enable the config */
  63         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  64                 (1 << 6)), &cs->config7);
  65         sdelay(2000);
  66 }
  67
  68 /*****************************************************
  69  * gpmc_init(): init gpmc bus
  70  * Init GPMC for x16, MuxMode (SDRAM in x32).
  71  * This code can only be executed from SRAM or SDRAM.
  72  *****************************************************/
  73 void gpmc_init(void)
  74 {
  75         /* putting a blanket check on GPMC based on ZeBu for now */
  76         gpmc_cfg = (struct gpmc *)GPMC_BASE;
  77
  78 #ifdef CONFIG_CMD_NAND
  79         const u32 *gpmc_config = NULL;
  80         u32 base = 0;
  81         u32 size = 0;
  82 #endif
  83         /* global settings */
  84         writel(0x00000008, &gpmc_cfg->sysconfig);
  85         writel(0x00000100, &gpmc_cfg->irqstatus);
  86         writel(0x00000100, &gpmc_cfg->irqenable);
  87         writel(0x00000012, &gpmc_cfg->config);
  88         /*
  89          * Disable the GPMC0 config set by ROM code
  90          */
  91         writel(0, &gpmc_cfg->cs[0].config7);
  92         sdelay(1000);
  93
  94 #ifdef CONFIG_CMD_NAND
  95         gpmc_config = gpmc_m_nand;
  96
  97         base = PISMO1_NAND_BASE;
  98         size = PISMO1_NAND_SIZE;
  99         enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 100 #endif
 101 }