arch/arm/cpu/armv7/am33xx/mem.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Mansoor Ahamed <mansoor.ahamed@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Manikandan Pillai <mani.pillai@ti.com>
  10  *     Richard Woodruff <r-woodruff2@ti.com>
  11  *     Syed Mohammed Khasim <khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/mem.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <command.h>
  22
  23 struct gpmc *gpmc_cfg;
  24
  25 #if defined(CONFIG_CMD_NAND)
  26 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  27         M_NAND_GPMC_CONFIG1,
  28         M_NAND_GPMC_CONFIG2,
  29         M_NAND_GPMC_CONFIG3,
  30         M_NAND_GPMC_CONFIG4,
  31         M_NAND_GPMC_CONFIG5,
  32         M_NAND_GPMC_CONFIG6, 0
  33 };
  34 #endif
  35
  36
  37 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  38                         u32 size)
  39 {
  40         writel(0, &cs->config7);
  41         sdelay(1000);
  42         /* Delay for settling */
  43         writel(gpmc_config[0], &cs->config1);
  44         writel(gpmc_config[1], &cs->config2);
  45         writel(gpmc_config[2], &cs->config3);
  46         writel(gpmc_config[3], &cs->config4);
  47         writel(gpmc_config[4], &cs->config5);
  48         writel(gpmc_config[5], &cs->config6);
  49         /* Enable the config */
  50         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  51                 (1 << 6)), &cs->config7);
  52         sdelay(2000);
  53 }
  54
  55 /*****************************************************
  56  * gpmc_init(): init gpmc bus
  57  * Init GPMC for x16, MuxMode (SDRAM in x32).
  58  * This code can only be executed from SRAM or SDRAM.
  59  *****************************************************/
  60 void gpmc_init(void)
  61 {
  62         /* putting a blanket check on GPMC based on ZeBu for now */
  63         gpmc_cfg = (struct gpmc *)GPMC_BASE;
  64
  65 #ifdef CONFIG_CMD_NAND
  66         const u32 *gpmc_config = NULL;
  67         u32 base = 0;
  68         u32 size = 0;
  69 #endif
  70         /* global settings */
  71         writel(0x00000008, &gpmc_cfg->sysconfig);
  72         writel(0x00000100, &gpmc_cfg->irqstatus);
  73         writel(0x00000100, &gpmc_cfg->irqenable);
  74         writel(0x00000012, &gpmc_cfg->config);
  75         /*
  76          * Disable the GPMC0 config set by ROM code
  77          */
  78         writel(0, &gpmc_cfg->cs[0].config7);
  79         sdelay(1000);
  80
  81 #ifdef CONFIG_CMD_NAND
  82         gpmc_config = gpmc_m_nand;
  83
  84         base = PISMO1_NAND_BASE;
  85         size = PISMO1_NAND_SIZE;
  86         enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
  87 #endif
  88 }