]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/am33xx/mem.c
3 * Texas Instruments, <www.ti.com>
6 * Mansoor Ahamed <mansoor.ahamed@ti.com>
9 * Manikandan Pillai <mani.pillai@ti.com>
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/mem.h>
20 #include <asm/arch/sys_proto.h>
23 struct gpmc
*gpmc_cfg
;
25 #if defined(CONFIG_CMD_NAND)
26 static const u32 gpmc_m_nand
[GPMC_MAX_REG
] = {
32 M_NAND_GPMC_CONFIG6
, 0
37 void enable_gpmc_cs_config(const u32
*gpmc_config
, struct gpmc_cs
*cs
, u32 base
,
40 writel(0, &cs
->config7
);
42 /* Delay for settling */
43 writel(gpmc_config
[0], &cs
->config1
);
44 writel(gpmc_config
[1], &cs
->config2
);
45 writel(gpmc_config
[2], &cs
->config3
);
46 writel(gpmc_config
[3], &cs
->config4
);
47 writel(gpmc_config
[4], &cs
->config5
);
48 writel(gpmc_config
[5], &cs
->config6
);
49 /* Enable the config */
50 writel((((size
& 0xF) << 8) | ((base
>> 24) & 0x3F) |
51 (1 << 6)), &cs
->config7
);
55 /*****************************************************
56 * gpmc_init(): init gpmc bus
57 * Init GPMC for x16, MuxMode (SDRAM in x32).
58 * This code can only be executed from SRAM or SDRAM.
59 *****************************************************/
62 /* putting a blanket check on GPMC based on ZeBu for now */
63 gpmc_cfg
= (struct gpmc
*)GPMC_BASE
;
65 #ifdef CONFIG_CMD_NAND
66 const u32
*gpmc_config
= NULL
;
71 writel(0x00000008, &gpmc_cfg
->sysconfig
);
72 writel(0x00000100, &gpmc_cfg
->irqstatus
);
73 writel(0x00000100, &gpmc_cfg
->irqenable
);
74 writel(0x00000012, &gpmc_cfg
->config
);
76 * Disable the GPMC0 config set by ROM code
78 writel(0, &gpmc_cfg
->cs
[0].config7
);
81 #ifdef CONFIG_CMD_NAND
82 gpmc_config
= gpmc_m_nand
;
84 base
= PISMO1_NAND_BASE
;
85 size
= PISMO1_NAND_SIZE
;
86 enable_gpmc_cs_config(gpmc_config
, &gpmc_cfg
->cs
[0], base
, size
);