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[people/ms/u-boot.git] / arch / arm / cpu / armv7 / exynos / pinmux.c
1 /*
2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <fdtdec.h>
10 #include <asm/arch/gpio.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/sromc.h>
13
14 static void exynos5_uart_config(int peripheral)
15 {
16 int i, start, count;
17
18 switch (peripheral) {
19 case PERIPH_ID_UART0:
20 start = EXYNOS5_GPIO_A00;
21 count = 4;
22 break;
23 case PERIPH_ID_UART1:
24 start = EXYNOS5_GPIO_D00;
25 count = 4;
26 break;
27 case PERIPH_ID_UART2:
28 start = EXYNOS5_GPIO_A10;
29 count = 4;
30 break;
31 case PERIPH_ID_UART3:
32 start = EXYNOS5_GPIO_A14;
33 count = 2;
34 break;
35 default:
36 debug("%s: invalid peripheral %d", __func__, peripheral);
37 return;
38 }
39 for (i = start; i < start + count; i++) {
40 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
41 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
42 }
43 }
44
45 static void exynos5420_uart_config(int peripheral)
46 {
47 int i, start, count;
48
49 switch (peripheral) {
50 case PERIPH_ID_UART0:
51 start = EXYNOS5420_GPIO_A00;
52 count = 4;
53 break;
54 case PERIPH_ID_UART1:
55 start = EXYNOS5420_GPIO_A04;
56 count = 4;
57 break;
58 case PERIPH_ID_UART2:
59 start = EXYNOS5420_GPIO_A10;
60 count = 4;
61 break;
62 case PERIPH_ID_UART3:
63 start = EXYNOS5420_GPIO_A14;
64 count = 2;
65 break;
66 default:
67 debug("%s: invalid peripheral %d", __func__, peripheral);
68 return;
69 }
70
71 for (i = start; i < start + count; i++) {
72 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
73 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
74 }
75 }
76
77 static int exynos5_mmc_config(int peripheral, int flags)
78 {
79 int i, start, start_ext, gpio_func = 0;
80
81 switch (peripheral) {
82 case PERIPH_ID_SDMMC0:
83 start = EXYNOS5_GPIO_C00;
84 start_ext = EXYNOS5_GPIO_C10;
85 gpio_func = S5P_GPIO_FUNC(0x2);
86 break;
87 case PERIPH_ID_SDMMC1:
88 start = EXYNOS5_GPIO_C20;
89 start_ext = 0;
90 break;
91 case PERIPH_ID_SDMMC2:
92 start = EXYNOS5_GPIO_C30;
93 start_ext = EXYNOS5_GPIO_C43;
94 gpio_func = S5P_GPIO_FUNC(0x3);
95 break;
96 case PERIPH_ID_SDMMC3:
97 start = EXYNOS5_GPIO_C40;
98 start_ext = 0;
99 break;
100 default:
101 debug("%s: invalid peripheral %d", __func__, peripheral);
102 return -1;
103 }
104 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
105 debug("SDMMC device %d does not support 8bit mode",
106 peripheral);
107 return -1;
108 }
109 if (flags & PINMUX_FLAG_8BIT_MODE) {
110 for (i = start_ext; i <= (start_ext + 3); i++) {
111 gpio_cfg_pin(i, gpio_func);
112 gpio_set_pull(i, S5P_GPIO_PULL_UP);
113 gpio_set_drv(i, S5P_GPIO_DRV_4X);
114 }
115 }
116 for (i = start; i < (start + 2); i++) {
117 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
118 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
119 gpio_set_drv(i, S5P_GPIO_DRV_4X);
120 }
121 for (i = (start + 3); i <= (start + 6); i++) {
122 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
123 gpio_set_pull(i, S5P_GPIO_PULL_UP);
124 gpio_set_drv(i, S5P_GPIO_DRV_4X);
125 }
126
127 return 0;
128 }
129
130 static int exynos5420_mmc_config(int peripheral, int flags)
131 {
132 int i, start = 0, start_ext = 0;
133
134 switch (peripheral) {
135 case PERIPH_ID_SDMMC0:
136 start = EXYNOS5420_GPIO_C00;
137 start_ext = EXYNOS5420_GPIO_C30;
138 break;
139 case PERIPH_ID_SDMMC1:
140 start = EXYNOS5420_GPIO_C10;
141 start_ext = EXYNOS5420_GPIO_D14;
142 break;
143 case PERIPH_ID_SDMMC2:
144 start = EXYNOS5420_GPIO_C20;
145 start_ext = 0;
146 break;
147 default:
148 start = 0;
149 debug("%s: invalid peripheral %d", __func__, peripheral);
150 return -1;
151 }
152
153 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
154 debug("SDMMC device %d does not support 8bit mode",
155 peripheral);
156 return -1;
157 }
158
159 if (flags & PINMUX_FLAG_8BIT_MODE) {
160 for (i = start_ext; i <= (start_ext + 3); i++) {
161 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
162 gpio_set_pull(i, S5P_GPIO_PULL_UP);
163 gpio_set_drv(i, S5P_GPIO_DRV_4X);
164 }
165 }
166
167 for (i = start; i < (start + 3); i++) {
168 /*
169 * MMC0 is intended to be used for eMMC. The
170 * card detect pin is used as a VDDEN signal to
171 * power on the eMMC. The 5420 iROM makes
172 * this same assumption.
173 */
174 if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
175 gpio_set_value(i, 1);
176 gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
177 } else {
178 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
179 }
180 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
181 gpio_set_drv(i, S5P_GPIO_DRV_4X);
182 }
183
184 for (i = (start + 3); i <= (start + 6); i++) {
185 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
186 gpio_set_pull(i, S5P_GPIO_PULL_UP);
187 gpio_set_drv(i, S5P_GPIO_DRV_4X);
188 }
189
190 return 0;
191 }
192
193 static void exynos5_sromc_config(int flags)
194 {
195 int i;
196
197 /*
198 * SROM:CS1 and EBI
199 *
200 * GPY0[0] SROM_CSn[0]
201 * GPY0[1] SROM_CSn[1](2)
202 * GPY0[2] SROM_CSn[2]
203 * GPY0[3] SROM_CSn[3]
204 * GPY0[4] EBI_OEn(2)
205 * GPY0[5] EBI_EEn(2)
206 *
207 * GPY1[0] EBI_BEn[0](2)
208 * GPY1[1] EBI_BEn[1](2)
209 * GPY1[2] SROM_WAIT(2)
210 * GPY1[3] EBI_DATA_RDn(2)
211 */
212 gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
213 S5P_GPIO_FUNC(2));
214 gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
215 gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
216
217 for (i = 0; i < 4; i++)
218 gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
219
220 /*
221 * EBI: 8 Addrss Lines
222 *
223 * GPY3[0] EBI_ADDR[0](2)
224 * GPY3[1] EBI_ADDR[1](2)
225 * GPY3[2] EBI_ADDR[2](2)
226 * GPY3[3] EBI_ADDR[3](2)
227 * GPY3[4] EBI_ADDR[4](2)
228 * GPY3[5] EBI_ADDR[5](2)
229 * GPY3[6] EBI_ADDR[6](2)
230 * GPY3[7] EBI_ADDR[7](2)
231 *
232 * EBI: 16 Data Lines
233 *
234 * GPY5[0] EBI_DATA[0](2)
235 * GPY5[1] EBI_DATA[1](2)
236 * GPY5[2] EBI_DATA[2](2)
237 * GPY5[3] EBI_DATA[3](2)
238 * GPY5[4] EBI_DATA[4](2)
239 * GPY5[5] EBI_DATA[5](2)
240 * GPY5[6] EBI_DATA[6](2)
241 * GPY5[7] EBI_DATA[7](2)
242 *
243 * GPY6[0] EBI_DATA[8](2)
244 * GPY6[1] EBI_DATA[9](2)
245 * GPY6[2] EBI_DATA[10](2)
246 * GPY6[3] EBI_DATA[11](2)
247 * GPY6[4] EBI_DATA[12](2)
248 * GPY6[5] EBI_DATA[13](2)
249 * GPY6[6] EBI_DATA[14](2)
250 * GPY6[7] EBI_DATA[15](2)
251 */
252 for (i = 0; i < 8; i++) {
253 gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
254 gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
255
256 gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
257 gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
258
259 gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
260 gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
261 }
262 }
263
264 static void exynos5_i2c_config(int peripheral, int flags)
265 {
266 switch (peripheral) {
267 case PERIPH_ID_I2C0:
268 gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
269 gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
270 break;
271 case PERIPH_ID_I2C1:
272 gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
273 gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
274 break;
275 case PERIPH_ID_I2C2:
276 gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
277 gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
278 break;
279 case PERIPH_ID_I2C3:
280 gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
281 gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
282 break;
283 case PERIPH_ID_I2C4:
284 gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
285 gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
286 break;
287 case PERIPH_ID_I2C5:
288 gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
289 gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
290 break;
291 case PERIPH_ID_I2C6:
292 gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
293 gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
294 break;
295 case PERIPH_ID_I2C7:
296 gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
297 gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
298 break;
299 }
300 }
301
302 static void exynos5420_i2c_config(int peripheral)
303 {
304 switch (peripheral) {
305 case PERIPH_ID_I2C0:
306 gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
307 gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
308 break;
309 case PERIPH_ID_I2C1:
310 gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
311 gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
312 break;
313 case PERIPH_ID_I2C2:
314 gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
315 gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
316 break;
317 case PERIPH_ID_I2C3:
318 gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
319 gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
320 break;
321 case PERIPH_ID_I2C4:
322 gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
323 gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
324 break;
325 case PERIPH_ID_I2C5:
326 gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
327 gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
328 break;
329 case PERIPH_ID_I2C6:
330 gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
331 gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
332 break;
333 case PERIPH_ID_I2C7:
334 gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
335 gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
336 break;
337 case PERIPH_ID_I2C8:
338 gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
339 gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
340 break;
341 case PERIPH_ID_I2C9:
342 gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
343 gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
344 break;
345 case PERIPH_ID_I2C10:
346 gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
347 gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
348 break;
349 }
350 }
351
352 static void exynos5_i2s_config(int peripheral)
353 {
354 int i;
355
356 switch (peripheral) {
357 case PERIPH_ID_I2S0:
358 for (i = 0; i < 5; i++)
359 gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
360 break;
361 case PERIPH_ID_I2S1:
362 for (i = 0; i < 5; i++)
363 gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
364 break;
365 }
366 }
367
368 void exynos5_spi_config(int peripheral)
369 {
370 int cfg = 0, pin = 0, i;
371
372 switch (peripheral) {
373 case PERIPH_ID_SPI0:
374 cfg = S5P_GPIO_FUNC(0x2);
375 pin = EXYNOS5_GPIO_A20;
376 break;
377 case PERIPH_ID_SPI1:
378 cfg = S5P_GPIO_FUNC(0x2);
379 pin = EXYNOS5_GPIO_A24;
380 break;
381 case PERIPH_ID_SPI2:
382 cfg = S5P_GPIO_FUNC(0x5);
383 pin = EXYNOS5_GPIO_B11;
384 break;
385 case PERIPH_ID_SPI3:
386 cfg = S5P_GPIO_FUNC(0x2);
387 pin = EXYNOS5_GPIO_F10;
388 break;
389 case PERIPH_ID_SPI4:
390 for (i = 0; i < 2; i++) {
391 gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
392 gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
393 }
394 break;
395 }
396 if (peripheral != PERIPH_ID_SPI4) {
397 for (i = pin; i < pin + 4; i++)
398 gpio_cfg_pin(i, cfg);
399 }
400 }
401
402 void exynos5420_spi_config(int peripheral)
403 {
404 int cfg, pin, i;
405
406 switch (peripheral) {
407 case PERIPH_ID_SPI0:
408 pin = EXYNOS5420_GPIO_A20;
409 cfg = S5P_GPIO_FUNC(0x2);
410 break;
411 case PERIPH_ID_SPI1:
412 pin = EXYNOS5420_GPIO_A24;
413 cfg = S5P_GPIO_FUNC(0x2);
414 break;
415 case PERIPH_ID_SPI2:
416 pin = EXYNOS5420_GPIO_B11;
417 cfg = S5P_GPIO_FUNC(0x5);
418 break;
419 case PERIPH_ID_SPI3:
420 pin = EXYNOS5420_GPIO_F10;
421 cfg = S5P_GPIO_FUNC(0x2);
422 break;
423 case PERIPH_ID_SPI4:
424 cfg = 0;
425 pin = 0;
426 break;
427 default:
428 cfg = 0;
429 pin = 0;
430 debug("%s: invalid peripheral %d", __func__, peripheral);
431 return;
432 }
433
434 if (peripheral != PERIPH_ID_SPI4) {
435 for (i = pin; i < pin + 4; i++)
436 gpio_cfg_pin(i, cfg);
437 } else {
438 for (i = 0; i < 2; i++) {
439 gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
440 S5P_GPIO_FUNC(0x4));
441 gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
442 S5P_GPIO_FUNC(0x4));
443 }
444 }
445 }
446
447 static int exynos5_pinmux_config(int peripheral, int flags)
448 {
449 switch (peripheral) {
450 case PERIPH_ID_UART0:
451 case PERIPH_ID_UART1:
452 case PERIPH_ID_UART2:
453 case PERIPH_ID_UART3:
454 exynos5_uart_config(peripheral);
455 break;
456 case PERIPH_ID_SDMMC0:
457 case PERIPH_ID_SDMMC1:
458 case PERIPH_ID_SDMMC2:
459 case PERIPH_ID_SDMMC3:
460 return exynos5_mmc_config(peripheral, flags);
461 case PERIPH_ID_SROMC:
462 exynos5_sromc_config(flags);
463 break;
464 case PERIPH_ID_I2C0:
465 case PERIPH_ID_I2C1:
466 case PERIPH_ID_I2C2:
467 case PERIPH_ID_I2C3:
468 case PERIPH_ID_I2C4:
469 case PERIPH_ID_I2C5:
470 case PERIPH_ID_I2C6:
471 case PERIPH_ID_I2C7:
472 exynos5_i2c_config(peripheral, flags);
473 break;
474 case PERIPH_ID_I2S0:
475 case PERIPH_ID_I2S1:
476 exynos5_i2s_config(peripheral);
477 break;
478 case PERIPH_ID_SPI0:
479 case PERIPH_ID_SPI1:
480 case PERIPH_ID_SPI2:
481 case PERIPH_ID_SPI3:
482 case PERIPH_ID_SPI4:
483 exynos5_spi_config(peripheral);
484 break;
485 default:
486 debug("%s: invalid peripheral %d", __func__, peripheral);
487 return -1;
488 }
489
490 return 0;
491 }
492
493 static int exynos5420_pinmux_config(int peripheral, int flags)
494 {
495 switch (peripheral) {
496 case PERIPH_ID_UART0:
497 case PERIPH_ID_UART1:
498 case PERIPH_ID_UART2:
499 case PERIPH_ID_UART3:
500 exynos5420_uart_config(peripheral);
501 break;
502 case PERIPH_ID_SDMMC0:
503 case PERIPH_ID_SDMMC1:
504 case PERIPH_ID_SDMMC2:
505 case PERIPH_ID_SDMMC3:
506 return exynos5420_mmc_config(peripheral, flags);
507 case PERIPH_ID_SPI0:
508 case PERIPH_ID_SPI1:
509 case PERIPH_ID_SPI2:
510 case PERIPH_ID_SPI3:
511 case PERIPH_ID_SPI4:
512 exynos5420_spi_config(peripheral);
513 break;
514 case PERIPH_ID_I2C0:
515 case PERIPH_ID_I2C1:
516 case PERIPH_ID_I2C2:
517 case PERIPH_ID_I2C3:
518 case PERIPH_ID_I2C4:
519 case PERIPH_ID_I2C5:
520 case PERIPH_ID_I2C6:
521 case PERIPH_ID_I2C7:
522 case PERIPH_ID_I2C8:
523 case PERIPH_ID_I2C9:
524 case PERIPH_ID_I2C10:
525 exynos5420_i2c_config(peripheral);
526 break;
527 default:
528 debug("%s: invalid peripheral %d", __func__, peripheral);
529 return -1;
530 }
531
532 return 0;
533 }
534
535 static void exynos4_i2c_config(int peripheral, int flags)
536 {
537 switch (peripheral) {
538 case PERIPH_ID_I2C0:
539 gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
540 gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
541 break;
542 case PERIPH_ID_I2C1:
543 gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
544 gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
545 break;
546 case PERIPH_ID_I2C2:
547 gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
548 gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
549 break;
550 case PERIPH_ID_I2C3:
551 gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
552 gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
553 break;
554 case PERIPH_ID_I2C4:
555 gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
556 gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
557 break;
558 case PERIPH_ID_I2C5:
559 gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
560 gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
561 break;
562 case PERIPH_ID_I2C6:
563 gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
564 gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
565 break;
566 case PERIPH_ID_I2C7:
567 gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
568 gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
569 break;
570 }
571 }
572
573 static int exynos4_mmc_config(int peripheral, int flags)
574 {
575 int i, start = 0, start_ext = 0;
576 unsigned int func, ext_func;
577
578 switch (peripheral) {
579 case PERIPH_ID_SDMMC0:
580 start = EXYNOS4_GPIO_K00;
581 start_ext = EXYNOS4_GPIO_K13;
582 func = S5P_GPIO_FUNC(0x2);
583 ext_func = S5P_GPIO_FUNC(0x3);
584 break;
585 case PERIPH_ID_SDMMC2:
586 start = EXYNOS4_GPIO_K20;
587 start_ext = EXYNOS4_GPIO_K33;
588 func = S5P_GPIO_FUNC(0x2);
589 ext_func = S5P_GPIO_FUNC(0x3);
590 break;
591 case PERIPH_ID_SDMMC4:
592 start = EXYNOS4_GPIO_K00;
593 start_ext = EXYNOS4_GPIO_K13;
594 func = S5P_GPIO_FUNC(0x3);
595 ext_func = S5P_GPIO_FUNC(0x4);
596 break;
597 default:
598 return -1;
599 }
600 for (i = start; i < (start + 7); i++) {
601 if (i == (start + 2))
602 continue;
603 gpio_cfg_pin(i, func);
604 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
605 gpio_set_drv(i, S5P_GPIO_DRV_4X);
606 }
607 /* SDMMC2 do not use 8bit mode at exynos4 */
608 if (flags & PINMUX_FLAG_8BIT_MODE) {
609 for (i = start_ext; i < (start_ext + 4); i++) {
610 gpio_cfg_pin(i, ext_func);
611 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
612 gpio_set_drv(i, S5P_GPIO_DRV_4X);
613 }
614 }
615
616 return 0;
617 }
618
619 static void exynos4_uart_config(int peripheral)
620 {
621 int i, start, count;
622
623 switch (peripheral) {
624 case PERIPH_ID_UART0:
625 start = EXYNOS4_GPIO_A00;
626 count = 4;
627 break;
628 case PERIPH_ID_UART1:
629 start = EXYNOS4_GPIO_A04;
630 count = 4;
631 break;
632 case PERIPH_ID_UART2:
633 start = EXYNOS4_GPIO_A10;
634 count = 4;
635 break;
636 case PERIPH_ID_UART3:
637 start = EXYNOS4_GPIO_A14;
638 count = 2;
639 break;
640 default:
641 debug("%s: invalid peripheral %d", __func__, peripheral);
642 return;
643 }
644 for (i = start; i < (start + count); i++) {
645 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
646 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
647 }
648 }
649
650 static void exynos4x12_i2c_config(int peripheral, int flags)
651 {
652 switch (peripheral) {
653 case PERIPH_ID_I2C0:
654 gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
655 gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
656 break;
657 case PERIPH_ID_I2C1:
658 gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
659 gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
660 break;
661 case PERIPH_ID_I2C2:
662 gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
663 gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
664 break;
665 case PERIPH_ID_I2C3:
666 gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
667 gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
668 break;
669 case PERIPH_ID_I2C4:
670 gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
671 gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
672 break;
673 case PERIPH_ID_I2C5:
674 gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
675 gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
676 break;
677 case PERIPH_ID_I2C6:
678 gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
679 gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
680 break;
681 case PERIPH_ID_I2C7:
682 gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
683 gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
684 break;
685 }
686 }
687
688 static int exynos4x12_mmc_config(int peripheral, int flags)
689 {
690 int i, start = 0, start_ext = 0;
691 unsigned int func, ext_func;
692
693 switch (peripheral) {
694 case PERIPH_ID_SDMMC0:
695 start = EXYNOS4X12_GPIO_K00;
696 start_ext = EXYNOS4X12_GPIO_K13;
697 func = S5P_GPIO_FUNC(0x2);
698 ext_func = S5P_GPIO_FUNC(0x3);
699 break;
700 case PERIPH_ID_SDMMC2:
701 start = EXYNOS4X12_GPIO_K20;
702 start_ext = EXYNOS4X12_GPIO_K33;
703 func = S5P_GPIO_FUNC(0x2);
704 ext_func = S5P_GPIO_FUNC(0x3);
705 break;
706 case PERIPH_ID_SDMMC4:
707 start = EXYNOS4X12_GPIO_K00;
708 start_ext = EXYNOS4X12_GPIO_K13;
709 func = S5P_GPIO_FUNC(0x3);
710 ext_func = S5P_GPIO_FUNC(0x4);
711 break;
712 default:
713 return -1;
714 }
715 for (i = start; i < (start + 7); i++) {
716 if (i == (start + 2))
717 continue;
718 gpio_cfg_pin(i, func);
719 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
720 gpio_set_drv(i, S5P_GPIO_DRV_4X);
721 }
722 if (flags & PINMUX_FLAG_8BIT_MODE) {
723 for (i = start_ext; i < (start_ext + 4); i++) {
724 gpio_cfg_pin(i, ext_func);
725 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
726 gpio_set_drv(i, S5P_GPIO_DRV_4X);
727 }
728 }
729
730 return 0;
731 }
732
733 static void exynos4x12_uart_config(int peripheral)
734 {
735 int i, start, count;
736
737 switch (peripheral) {
738 case PERIPH_ID_UART0:
739 start = EXYNOS4X12_GPIO_A00;
740 count = 4;
741 break;
742 case PERIPH_ID_UART1:
743 start = EXYNOS4X12_GPIO_A04;
744 count = 4;
745 break;
746 case PERIPH_ID_UART2:
747 start = EXYNOS4X12_GPIO_A10;
748 count = 4;
749 break;
750 case PERIPH_ID_UART3:
751 start = EXYNOS4X12_GPIO_A14;
752 count = 2;
753 break;
754 default:
755 debug("%s: invalid peripheral %d", __func__, peripheral);
756 return;
757 }
758 for (i = start; i < (start + count); i++) {
759 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
760 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
761 }
762 }
763
764 static int exynos4_pinmux_config(int peripheral, int flags)
765 {
766 switch (peripheral) {
767 case PERIPH_ID_UART0:
768 case PERIPH_ID_UART1:
769 case PERIPH_ID_UART2:
770 case PERIPH_ID_UART3:
771 exynos4_uart_config(peripheral);
772 break;
773 case PERIPH_ID_I2C0:
774 case PERIPH_ID_I2C1:
775 case PERIPH_ID_I2C2:
776 case PERIPH_ID_I2C3:
777 case PERIPH_ID_I2C4:
778 case PERIPH_ID_I2C5:
779 case PERIPH_ID_I2C6:
780 case PERIPH_ID_I2C7:
781 exynos4_i2c_config(peripheral, flags);
782 break;
783 case PERIPH_ID_SDMMC0:
784 case PERIPH_ID_SDMMC2:
785 case PERIPH_ID_SDMMC4:
786 return exynos4_mmc_config(peripheral, flags);
787 case PERIPH_ID_SDMMC1:
788 case PERIPH_ID_SDMMC3:
789 debug("SDMMC device %d not implemented\n", peripheral);
790 return -1;
791 default:
792 debug("%s: invalid peripheral %d", __func__, peripheral);
793 return -1;
794 }
795
796 return 0;
797 }
798
799 static int exynos4x12_pinmux_config(int peripheral, int flags)
800 {
801 switch (peripheral) {
802 case PERIPH_ID_UART0:
803 case PERIPH_ID_UART1:
804 case PERIPH_ID_UART2:
805 case PERIPH_ID_UART3:
806 exynos4x12_uart_config(peripheral);
807 break;
808 case PERIPH_ID_I2C0:
809 case PERIPH_ID_I2C1:
810 case PERIPH_ID_I2C2:
811 case PERIPH_ID_I2C3:
812 case PERIPH_ID_I2C4:
813 case PERIPH_ID_I2C5:
814 case PERIPH_ID_I2C6:
815 case PERIPH_ID_I2C7:
816 exynos4x12_i2c_config(peripheral, flags);
817 break;
818 case PERIPH_ID_SDMMC0:
819 case PERIPH_ID_SDMMC2:
820 case PERIPH_ID_SDMMC4:
821 return exynos4x12_mmc_config(peripheral, flags);
822 case PERIPH_ID_SDMMC1:
823 case PERIPH_ID_SDMMC3:
824 debug("SDMMC device %d not implemented\n", peripheral);
825 return -1;
826 default:
827 debug("%s: invalid peripheral %d", __func__, peripheral);
828 return -1;
829 }
830
831 return 0;
832 }
833
834 int exynos_pinmux_config(int peripheral, int flags)
835 {
836 if (cpu_is_exynos5()) {
837 if (proid_is_exynos5420())
838 return exynos5420_pinmux_config(peripheral, flags);
839 else if (proid_is_exynos5250())
840 return exynos5_pinmux_config(peripheral, flags);
841 } else if (cpu_is_exynos4()) {
842 if (proid_is_exynos4412())
843 return exynos4x12_pinmux_config(peripheral, flags);
844 else
845 return exynos4_pinmux_config(peripheral, flags);
846 }
847
848 debug("pinmux functionality not supported\n");
849
850 return -1;
851 }
852
853 #ifdef CONFIG_OF_CONTROL
854 static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
855 {
856 int err;
857 u32 cell[3];
858
859 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
860 ARRAY_SIZE(cell));
861 if (err) {
862 debug(" invalid peripheral id\n");
863 return PERIPH_ID_NONE;
864 }
865
866 return cell[1];
867 }
868
869 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
870 {
871 int err;
872 u32 cell[3];
873
874 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
875 ARRAY_SIZE(cell));
876 if (err)
877 return PERIPH_ID_NONE;
878
879 return cell[1];
880 }
881
882 int pinmux_decode_periph_id(const void *blob, int node)
883 {
884 if (cpu_is_exynos5())
885 return exynos5_pinmux_decode_periph_id(blob, node);
886 else if (cpu_is_exynos4())
887 return exynos4_pinmux_decode_periph_id(blob, node);
888
889 return PERIPH_ID_NONE;
890 }
891 #endif
"Das U-Boot" Source Tree