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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/exynos/pinmux.c
2 * Copyright (c) 2012 Samsung Electronics.
3 * Abhilash Kesavan <a.kesavan@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/pinmux.h>
27 #include <asm/arch/sromc.h>
29 static void exynos5_uart_config(int peripheral
)
31 struct exynos5_gpio_part1
*gpio1
=
32 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
33 struct s5p_gpio_bank
*bank
;
58 for (i
= start
; i
< start
+ count
; i
++) {
59 s5p_gpio_set_pull(bank
, i
, GPIO_PULL_NONE
);
60 s5p_gpio_cfg_pin(bank
, i
, GPIO_FUNC(0x2));
64 static int exynos5_mmc_config(int peripheral
, int flags
)
66 struct exynos5_gpio_part1
*gpio1
=
67 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
68 struct s5p_gpio_bank
*bank
, *bank_ext
;
69 int i
, start
= 0, gpio_func
= 0;
72 case PERIPH_ID_SDMMC0
:
74 bank_ext
= &gpio1
->c1
;
76 gpio_func
= GPIO_FUNC(0x2);
78 case PERIPH_ID_SDMMC1
:
82 case PERIPH_ID_SDMMC2
:
84 bank_ext
= &gpio1
->c4
;
86 gpio_func
= GPIO_FUNC(0x3);
88 case PERIPH_ID_SDMMC3
:
93 if ((flags
& PINMUX_FLAG_8BIT_MODE
) && !bank_ext
) {
94 debug("SDMMC device %d does not support 8bit mode",
98 if (flags
& PINMUX_FLAG_8BIT_MODE
) {
99 for (i
= start
; i
<= (start
+ 3); i
++) {
100 s5p_gpio_cfg_pin(bank_ext
, i
, gpio_func
);
101 s5p_gpio_set_pull(bank_ext
, i
, GPIO_PULL_UP
);
102 s5p_gpio_set_drv(bank_ext
, i
, GPIO_DRV_4X
);
105 for (i
= 0; i
< 2; i
++) {
106 s5p_gpio_cfg_pin(bank
, i
, GPIO_FUNC(0x2));
107 s5p_gpio_set_pull(bank
, i
, GPIO_PULL_NONE
);
108 s5p_gpio_set_drv(bank
, i
, GPIO_DRV_4X
);
110 for (i
= 3; i
<= 6; i
++) {
111 s5p_gpio_cfg_pin(bank
, i
, GPIO_FUNC(0x2));
112 s5p_gpio_set_pull(bank
, i
, GPIO_PULL_UP
);
113 s5p_gpio_set_drv(bank
, i
, GPIO_DRV_4X
);
119 static void exynos5_sromc_config(int flags
)
121 struct exynos5_gpio_part1
*gpio1
=
122 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
128 * GPY0[0] SROM_CSn[0]
129 * GPY0[1] SROM_CSn[1](2)
130 * GPY0[2] SROM_CSn[2]
131 * GPY0[3] SROM_CSn[3]
135 * GPY1[0] EBI_BEn[0](2)
136 * GPY1[1] EBI_BEn[1](2)
137 * GPY1[2] SROM_WAIT(2)
138 * GPY1[3] EBI_DATA_RDn(2)
140 s5p_gpio_cfg_pin(&gpio1
->y0
, (flags
& PINMUX_FLAG_BANK
),
142 s5p_gpio_cfg_pin(&gpio1
->y0
, 4, GPIO_FUNC(2));
143 s5p_gpio_cfg_pin(&gpio1
->y0
, 5, GPIO_FUNC(2));
145 for (i
= 0; i
< 4; i
++)
146 s5p_gpio_cfg_pin(&gpio1
->y1
, i
, GPIO_FUNC(2));
149 * EBI: 8 Addrss Lines
151 * GPY3[0] EBI_ADDR[0](2)
152 * GPY3[1] EBI_ADDR[1](2)
153 * GPY3[2] EBI_ADDR[2](2)
154 * GPY3[3] EBI_ADDR[3](2)
155 * GPY3[4] EBI_ADDR[4](2)
156 * GPY3[5] EBI_ADDR[5](2)
157 * GPY3[6] EBI_ADDR[6](2)
158 * GPY3[7] EBI_ADDR[7](2)
162 * GPY5[0] EBI_DATA[0](2)
163 * GPY5[1] EBI_DATA[1](2)
164 * GPY5[2] EBI_DATA[2](2)
165 * GPY5[3] EBI_DATA[3](2)
166 * GPY5[4] EBI_DATA[4](2)
167 * GPY5[5] EBI_DATA[5](2)
168 * GPY5[6] EBI_DATA[6](2)
169 * GPY5[7] EBI_DATA[7](2)
171 * GPY6[0] EBI_DATA[8](2)
172 * GPY6[1] EBI_DATA[9](2)
173 * GPY6[2] EBI_DATA[10](2)
174 * GPY6[3] EBI_DATA[11](2)
175 * GPY6[4] EBI_DATA[12](2)
176 * GPY6[5] EBI_DATA[13](2)
177 * GPY6[6] EBI_DATA[14](2)
178 * GPY6[7] EBI_DATA[15](2)
180 for (i
= 0; i
< 8; i
++) {
181 s5p_gpio_cfg_pin(&gpio1
->y3
, i
, GPIO_FUNC(2));
182 s5p_gpio_set_pull(&gpio1
->y3
, i
, GPIO_PULL_UP
);
184 s5p_gpio_cfg_pin(&gpio1
->y5
, i
, GPIO_FUNC(2));
185 s5p_gpio_set_pull(&gpio1
->y5
, i
, GPIO_PULL_UP
);
187 s5p_gpio_cfg_pin(&gpio1
->y6
, i
, GPIO_FUNC(2));
188 s5p_gpio_set_pull(&gpio1
->y6
, i
, GPIO_PULL_UP
);
192 static void exynos5_i2c_config(int peripheral
, int flags
)
195 struct exynos5_gpio_part1
*gpio1
=
196 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
198 switch (peripheral
) {
200 s5p_gpio_cfg_pin(&gpio1
->b3
, 0, GPIO_FUNC(0x2));
201 s5p_gpio_cfg_pin(&gpio1
->b3
, 1, GPIO_FUNC(0x2));
204 s5p_gpio_cfg_pin(&gpio1
->b3
, 2, GPIO_FUNC(0x2));
205 s5p_gpio_cfg_pin(&gpio1
->b3
, 3, GPIO_FUNC(0x2));
208 s5p_gpio_cfg_pin(&gpio1
->a0
, 6, GPIO_FUNC(0x3));
209 s5p_gpio_cfg_pin(&gpio1
->a0
, 7, GPIO_FUNC(0x3));
212 s5p_gpio_cfg_pin(&gpio1
->a1
, 2, GPIO_FUNC(0x3));
213 s5p_gpio_cfg_pin(&gpio1
->a1
, 3, GPIO_FUNC(0x3));
216 s5p_gpio_cfg_pin(&gpio1
->a2
, 0, GPIO_FUNC(0x3));
217 s5p_gpio_cfg_pin(&gpio1
->a2
, 1, GPIO_FUNC(0x3));
220 s5p_gpio_cfg_pin(&gpio1
->a2
, 2, GPIO_FUNC(0x3));
221 s5p_gpio_cfg_pin(&gpio1
->a2
, 3, GPIO_FUNC(0x3));
224 s5p_gpio_cfg_pin(&gpio1
->b1
, 3, GPIO_FUNC(0x4));
225 s5p_gpio_cfg_pin(&gpio1
->b1
, 4, GPIO_FUNC(0x4));
228 s5p_gpio_cfg_pin(&gpio1
->b2
, 2, GPIO_FUNC(0x3));
229 s5p_gpio_cfg_pin(&gpio1
->b2
, 3, GPIO_FUNC(0x3));
234 static void exynos5_i2s_config(int peripheral
)
237 struct exynos5_gpio_part1
*gpio1
=
238 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
240 for (i
= 0; i
< 5; i
++)
241 s5p_gpio_cfg_pin(&gpio1
->b0
, i
, GPIO_FUNC(0x02));
244 void exynos5_spi_config(int peripheral
)
246 int cfg
= 0, pin
= 0, i
;
247 struct s5p_gpio_bank
*bank
= NULL
;
248 struct exynos5_gpio_part1
*gpio1
=
249 (struct exynos5_gpio_part1
*) samsung_get_base_gpio_part1();
250 struct exynos5_gpio_part2
*gpio2
=
251 (struct exynos5_gpio_part2
*) samsung_get_base_gpio_part2();
253 switch (peripheral
) {
256 cfg
= GPIO_FUNC(0x2);
261 cfg
= GPIO_FUNC(0x2);
266 cfg
= GPIO_FUNC(0x5);
271 cfg
= GPIO_FUNC(0x2);
275 for (i
= 0; i
< 2; i
++) {
276 s5p_gpio_cfg_pin(&gpio2
->f0
, i
+ 2, GPIO_FUNC(0x4));
277 s5p_gpio_cfg_pin(&gpio2
->e0
, i
+ 4, GPIO_FUNC(0x4));
281 if (peripheral
!= PERIPH_ID_SPI4
) {
282 for (i
= pin
; i
< pin
+ 4; i
++)
283 s5p_gpio_cfg_pin(bank
, i
, cfg
);
287 static int exynos5_pinmux_config(int peripheral
, int flags
)
289 switch (peripheral
) {
290 case PERIPH_ID_UART0
:
291 case PERIPH_ID_UART1
:
292 case PERIPH_ID_UART2
:
293 case PERIPH_ID_UART3
:
294 exynos5_uart_config(peripheral
);
296 case PERIPH_ID_SDMMC0
:
297 case PERIPH_ID_SDMMC1
:
298 case PERIPH_ID_SDMMC2
:
299 case PERIPH_ID_SDMMC3
:
300 return exynos5_mmc_config(peripheral
, flags
);
301 case PERIPH_ID_SROMC
:
302 exynos5_sromc_config(flags
);
312 exynos5_i2c_config(peripheral
, flags
);
315 exynos5_i2s_config(peripheral
);
322 exynos5_spi_config(peripheral
);
325 debug("%s: invalid peripheral %d", __func__
, peripheral
);
332 static int exynos4_mmc_config(int peripheral
, int flags
)
334 struct exynos4_gpio_part2
*gpio2
=
335 (struct exynos4_gpio_part2
*)samsung_get_base_gpio_part2();
336 struct s5p_gpio_bank
*bank
, *bank_ext
;
339 switch (peripheral
) {
340 case PERIPH_ID_SDMMC0
:
342 bank_ext
= &gpio2
->k1
;
344 case PERIPH_ID_SDMMC2
:
346 bank_ext
= &gpio2
->k3
;
351 for (i
= 0; i
< 7; i
++) {
354 s5p_gpio_cfg_pin(bank
, i
, GPIO_FUNC(0x2));
355 s5p_gpio_set_pull(bank
, i
, GPIO_PULL_NONE
);
356 s5p_gpio_set_drv(bank
, i
, GPIO_DRV_4X
);
358 if (flags
& PINMUX_FLAG_8BIT_MODE
) {
359 for (i
= 3; i
< 7; i
++) {
360 s5p_gpio_cfg_pin(bank_ext
, i
, GPIO_FUNC(0x3));
361 s5p_gpio_set_pull(bank_ext
, i
, GPIO_PULL_NONE
);
362 s5p_gpio_set_drv(bank_ext
, i
, GPIO_DRV_4X
);
369 static int exynos4_pinmux_config(int peripheral
, int flags
)
371 switch (peripheral
) {
372 case PERIPH_ID_SDMMC0
:
373 case PERIPH_ID_SDMMC2
:
374 return exynos4_mmc_config(peripheral
, flags
);
375 case PERIPH_ID_SDMMC1
:
376 case PERIPH_ID_SDMMC3
:
377 case PERIPH_ID_SDMMC4
:
378 printf("SDMMC device %d not implemented\n", peripheral
);
381 debug("%s: invalid peripheral %d", __func__
, peripheral
);
388 int exynos_pinmux_config(int peripheral
, int flags
)
390 if (cpu_is_exynos5())
391 return exynos5_pinmux_config(peripheral
, flags
);
392 else if (cpu_is_exynos4())
393 return exynos4_pinmux_config(peripheral
, flags
);
395 debug("pinmux functionality not supported\n");