arch/arm/cpu/armv7/ls102xa/Kconfig

   1 config ARCH_LS1021A
   2         bool
   3         select SYS_FSL_ERRATUM_A010315
   4         select SYS_FSL_SRDS_1
   5         select SYS_HAS_SERDES
   6
   7 menu "LS102xA architecture"
   8         depends on ARCH_LS1021A
   9
  10 config LS1_DEEP_SLEEP
  11         bool "Deep sleep"
  12         depends on ARCH_LS1021A
  13
  14 config MAX_CPUS
  15         int "Maximum number of CPUs permitted for LS102xA"
  16         depends on ARCH_LS1021A
  17         default 2
  18         help
  19           Set this number to the maximum number of possible CPUs in the SoC.
  20           SoCs may have multiple clusters with each cluster may have multiple
  21           ports. If some ports are reserved but higher ports are used for
  22           cores, count the reserved ports. This will allocate enough memory
  23           in spin table to properly handle all cores.
  24
  25 config SYS_FSL_ERRATUM_A010315
  26         bool "Workaround for PCIe erratum A010315"
  27
  28 config SYS_FSL_SRDS_1
  29         bool
  30
  31 config SYS_FSL_SRDS_2
  32         bool
  33
  34 config SYS_HAS_SERDES
  35         bool
  36
  37 config SYS_FSL_IFC_BANK_COUNT
  38         int "Maximum banks of Integrated flash controller"
  39         depends on ARCH_LS1021A
  40         default 8
  41
  42 endmenu