arch/arm/cpu/armv7/ls102xa/Kconfig

   1 config ARCH_LS1021A
   2         bool
   3         select SYS_FSL_ERRATUM_A008378
   4         select SYS_FSL_ERRATUM_A008407
   5         select SYS_FSL_ERRATUM_A008997
   6         select SYS_FSL_ERRATUM_A009007
   7         select SYS_FSL_ERRATUM_A009008
   8         select SYS_FSL_ERRATUM_A009663
   9         select SYS_FSL_ERRATUM_A009798
  10         select SYS_FSL_ERRATUM_A009942
  11         select SYS_FSL_ERRATUM_A010315
  12         select SYS_FSL_HAS_CCI400
  13         select SYS_FSL_SRDS_1
  14         select SYS_HAS_SERDES
  15         select SYS_FSL_DDR_BE if SYS_FSL_DDR
  16         select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
  17         select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
  18         select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
  19         select SYS_FSL_HAS_SEC
  20         select SYS_FSL_SEC_COMPAT_5
  21         select SYS_FSL_SEC_LE
  22         imply SCSI
  23         imply SCSI_AHCI
  24         imply CMD_PCI
  25
  26 menu "LS102xA architecture"
  27         depends on ARCH_LS1021A
  28
  29 config FSL_PCIE_COMPAT
  30         string "PCIe compatible of Kernel DT"
  31         depends on PCIE_LAYERSCAPE
  32         default "fsl,ls1021a-pcie" if ARCH_LS1021A
  33         help
  34           This compatible is used to find pci controller node in Kernel DT
  35           to complete fixup.
  36
  37 config LS1_DEEP_SLEEP
  38         bool "Deep sleep"
  39         depends on ARCH_LS1021A
  40
  41 config MAX_CPUS
  42         int "Maximum number of CPUs permitted for LS102xA"
  43         depends on ARCH_LS1021A
  44         default 2
  45         help
  46           Set this number to the maximum number of possible CPUs in the SoC.
  47           SoCs may have multiple clusters with each cluster may have multiple
  48           ports. If some ports are reserved but higher ports are used for
  49           cores, count the reserved ports. This will allocate enough memory
  50           in spin table to properly handle all cores.
  51
  52 config SECURE_BOOT
  53         bool    "Secure Boot"
  54         help
  55                 Enable Freescale Secure Boot feature. Normally selected
  56                 by defconfig. If unsure, do not change.
  57
  58 config SYS_CCI400_OFFSET
  59         hex "Offset for CCI400 base"
  60         depends on SYS_FSL_HAS_CCI400
  61         default 0x180000
  62         help
  63           Offset for CCI400 base.
  64           CCI400 base addr = CCSRBAR + CCI400_OFFSET
  65
  66 config SYS_FSL_ERRATUM_A008997
  67         bool
  68         help
  69           Workaround for USB PHY erratum A008997
  70
  71 config SYS_FSL_ERRATUM_A009007
  72         bool
  73         help
  74           Workaround for USB PHY erratum A009007
  75
  76 config SYS_FSL_ERRATUM_A009008
  77         bool
  78         help
  79           Workaround for USB PHY erratum A009008
  80
  81 config SYS_FSL_ERRATUM_A009798
  82         bool
  83         help
  84           Workaround for USB PHY erratum A009798
  85
  86 config SYS_FSL_ERRATUM_A010315
  87         bool "Workaround for PCIe erratum A010315"
  88
  89 config SYS_FSL_HAS_CCI400
  90         bool
  91
  92 config SYS_FSL_SRDS_1
  93         bool
  94
  95 config SYS_FSL_SRDS_2
  96         bool
  97
  98 config SYS_HAS_SERDES
  99         bool
 100
 101 config SYS_FSL_IFC_BANK_COUNT
 102         int "Maximum banks of Integrated flash controller"
 103         depends on ARCH_LS1021A
 104         default 8
 105
 106 config SYS_FSL_ERRATUM_A008407
 107         bool
 108
 109 endmenu