arch/arm/cpu/armv7/ls102xa/cpu.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <tsec.h>
  12 #include <netdev.h>
  13 #include <fsl_esdhc.h>
  14
  15 #include "fsl_epu.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #if defined(CONFIG_DISPLAY_CPUINFO)
  20 int print_cpuinfo(void)
  21 {
  22         char buf1[32], buf2[32];
  23         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  24         unsigned int svr, major, minor, ver, i;
  25
  26         svr = in_be32(&gur->svr);
  27         major = SVR_MAJ(svr);
  28         minor = SVR_MIN(svr);
  29
  30         puts("CPU:   Freescale LayerScape ");
  31
  32         ver = SVR_SOC_VER(svr);
  33         switch (ver) {
  34         case SOC_VER_SLS1020:
  35                 puts("SLS1020");
  36                 break;
  37         case SOC_VER_LS1020:
  38                 puts("LS1020");
  39                 break;
  40         case SOC_VER_LS1021:
  41                 puts("LS1021");
  42                 break;
  43         case SOC_VER_LS1022:
  44                 puts("LS1022");
  45                 break;
  46         default:
  47                 puts("Unknown");
  48                 break;
  49         }
  50
  51         if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
  52                 puts("E");
  53
  54         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  55
  56         puts("Clock Configuration:");
  57
  58         printf("\n       CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
  59         printf("\n       Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
  60         printf("DDR:%-4s MHz (%s MT/s data rate), ",
  61                strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
  62         puts("\n");
  63
  64         /* Display the RCW, so that no one gets confused as to what RCW
  65          * we're actually using for this boot.
  66          */
  67         puts("Reset Configuration Word (RCW):");
  68         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  69                 u32 rcw = in_be32(&gur->rcwsr[i]);
  70
  71                 if ((i % 4) == 0)
  72                         printf("\n       %08x:", i * 4);
  73                 printf(" %08x", rcw);
  74         }
  75         puts("\n");
  76
  77         return 0;
  78 }
  79 #endif
  80
  81 void enable_caches(void)
  82 {
  83 #ifndef CONFIG_SYS_ICACHE_OFF
  84         icache_enable();
  85 #endif
  86 #ifndef CONFIG_SYS_DCACHE_OFF
  87         dcache_enable();
  88 #endif
  89 }
  90
  91 #ifdef CONFIG_FSL_ESDHC
  92 int cpu_mmc_init(bd_t *bis)
  93 {
  94         return fsl_esdhc_mmc_init(bis);
  95 }
  96 #endif
  97
  98 int cpu_eth_init(bd_t *bis)
  99 {
 100 #ifdef CONFIG_TSEC_ENET
 101         tsec_standard_init(bis);
 102 #endif
 103
 104         return 0;
 105 }
 106
 107 int arch_cpu_init(void)
 108 {
 109         void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 110
 111         /*
 112          * After wakeup from deep sleep, Clear EPU registers
 113          * as early as possible to prevent from possible issue.
 114          * It's also safe to clear at normal boot.
 115          */
 116         fsl_epu_clean(epu_base);
 117
 118         return 0;
 119 }
 120
 121 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
 122 /* Set the address at which the secondary core starts from.*/
 123 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 124 {
 125         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 126
 127         out_be32(&gur->scratchrw[0], addr);
 128 }
 129
 130 /* Release the secondary core from holdoff state and kick it */
 131 void smp_kick_all_cpus(void)
 132 {
 133         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 134
 135         out_be32(&gur->brrl, 0x2);
 136 }
 137 #endif