2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/processor.h>
12 #include <asm/arch/clock.h>
13 #include <linux/ctype.h>
14 #ifdef CONFIG_FSL_ESDHC
15 #include <fsl_esdhc.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 void ft_fixup_enet_phy_connect_type(void *fdt
)
23 struct eth_device
*dev
;
24 struct tsec_private
*priv
;
25 const char *enet_path
, *phy_path
;
33 while ((dev
= eth_get_dev_by_index(i
++)) != NULL
) {
34 if (strstr(dev
->name
, "eTSEC1"))
36 else if (strstr(dev
->name
, "eTSEC2"))
38 else if (strstr(dev
->name
, "eTSEC3"))
44 if (priv
->flags
& TSEC_SGMII
)
47 sprintf(enet
, "ethernet%d", enet_id
);
48 enet_path
= fdt_get_alias(fdt
, enet
);
52 sprintf(phy
, "enet%d_rgmii_phy", enet_id
);
53 phy_path
= fdt_get_alias(fdt
, phy
);
57 phy_node
= fdt_path_offset(fdt
, phy_path
);
61 ph
= fdt_create_phandle(fdt
, phy_node
);
63 do_fixup_by_path_u32(fdt
, enet_path
,
66 do_fixup_by_path(fdt
, enet_path
, "phy-connection-type",
67 phy_string_for_interface(
68 PHY_INTERFACE_MODE_RGMII_ID
),
69 sizeof(phy_string_for_interface(
70 PHY_INTERFACE_MODE_RGMII_ID
)),
75 void ft_cpu_setup(void *blob
, bd_t
*bd
)
79 const char *sysclk_path
;
81 unsigned long busclk
= get_bus_freq(0);
83 fdt_fixup_ethernet(blob
);
85 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
86 while (off
!= -FDT_ERR_NOTFOUND
) {
88 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
89 off
= fdt_node_offset_by_prop_value(blob
, off
,
90 "device_type", "cpu", 4);
93 do_fixup_by_prop_u32(blob
, "device_type", "soc",
94 4, "bus-frequency", busclk
/ 2, 1);
96 ft_fixup_enet_phy_connect_type(blob
);
98 #ifdef CONFIG_SYS_NS16550
99 do_fixup_by_compat_u32(blob
, "fsl,16550-FIFO64",
100 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
103 sysclk_path
= fdt_get_alias(blob
, "sysclk");
105 do_fixup_by_path_u32(blob
, sysclk_path
, "clock-frequency",
106 CONFIG_SYS_CLK_FREQ
, 1);
107 do_fixup_by_compat_u32(blob
, "fsl,qoriq-sysclk-2.0",
108 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
110 #if defined(CONFIG_FSL_ESDHC)
111 fdt_fixup_esdhc(blob
, bd
);
115 * platform bus clock = system bus clock/2
116 * Here busclk = system bus clock
117 * We are using the platform bus clock as 1588 Timer reference
118 * clock source select
120 do_fixup_by_compat_u32(blob
, "fsl, gianfar-ptp-timer",
121 "timer-frequency", busclk
/ 2, 1);
124 * clock-freq should change to clock-frequency and
125 * flexcan-v1.0 should change to p1010-flexcan respectively
128 do_fixup_by_compat_u32(blob
, "fsl, flexcan-v1.0",
129 "clock_freq", busclk
/ 2, 1);
131 do_fixup_by_compat_u32(blob
, "fsl, flexcan-v1.0",
132 "clock-frequency", busclk
/ 2, 1);
134 do_fixup_by_compat_u32(blob
, "fsl, ls1021a-flexcan",
135 "clock-frequency", busclk
/ 2, 1);