arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
   5  * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
   6  */
   7
   8 #include <config.h>
   9 #include <asm/io.h>
  10 #include <asm/psci.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <fsl_immap.h>
  13 #include "fsl_epu.h"
  14
  15 #define __secure __attribute__((section("._secure.text")))
  16
  17 #define CCSR_GICD_CTLR                  0x1000
  18 #define CCSR_GICC_CTLR                  0x2000
  19 #define DCSR_RCPM_CG1CR0                0x31c
  20 #define DCSR_RCPM_CSTTACR0              0xb00
  21 #define DCFG_CRSTSR_WDRFR               0x8
  22 #define DDR_RESV_LEN                    128
  23
  24 #ifdef CONFIG_LS1_DEEP_SLEEP
  25 /*
  26  * DDR controller initialization training breaks the first 128 bytes of DDR,
  27  * save them so that the bootloader can restore them while resuming.
  28  */
  29 static void __secure ls1_save_ddr_head(void)
  30 {
  31         const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
  32         char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
  33         struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  34         int i;
  35
  36         out_le32(&scfg->sparecr[2], dest);
  37
  38         for (i = 0; i < DDR_RESV_LEN; i++)
  39                 *dest++ = *src++;
  40 }
  41
  42 static void __secure ls1_fsm_setup(void)
  43 {
  44         void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  45         void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
  46
  47         out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
  48         out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
  49
  50         fsl_epu_setup((void *)dcsr_epu_base);
  51
  52         /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
  53         out_be32(dcsr_epu_base + EPECR0, 0x5);
  54         out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
  55 }
  56
  57 static void __secure ls1_deepsleep_irq_cfg(void)
  58 {
  59         struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  60         struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
  61         u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
  62
  63         /* Mask interrupts from GIC */
  64         out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
  65         out_be32(&rcpm->nirqoutr, 0x0ffffffff);
  66         /* Mask deep sleep wake-up interrupts while entering deep sleep */
  67         out_be32(&rcpm->dsimskr, 0x0ffffffff);
  68
  69         ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
  70         /*
  71          * Workaround: There is bug of register ippdexpcr1, when read it always
  72          * returns zero, so its value is saved to a scrachpad register to be
  73          * read, that is why we don't read it from register ippdexpcr1 itself.
  74          */
  75         ippdexpcr1 = in_le32(&scfg->sparecr[7]);
  76
  77         if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
  78                 pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
  79                              SCFG_PMCINTECR_ETSECRXG1 |
  80                              SCFG_PMCINTECR_ETSECERRG0 |
  81                              SCFG_PMCINTECR_ETSECERRG1;
  82
  83         if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
  84                 pmcintecr |= SCFG_PMCINTECR_GPIO;
  85
  86         if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
  87                 pmcintecr |= SCFG_PMCINTECR_LPUART;
  88
  89         if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
  90                 pmcintecr |= SCFG_PMCINTECR_FTM;
  91
  92         /* Always set external IRQ pins as wakeup source */
  93         pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
  94
  95         out_be32(&scfg->pmcintlecr, 0);
  96         /* Clear PMC interrupt status */
  97         out_be32(&scfg->pmcintsr, 0xffffffff);
  98         /* Enable wakeup interrupt during deep sleep */
  99         out_be32(&scfg->pmcintecr, pmcintecr);
 100 }
 101
 102 static void __secure ls1_delay(unsigned int loop)
 103 {
 104         while (loop--) {
 105                 int i = 1000;
 106                 while (i--)
 107                         ;
 108         }
 109 }
 110
 111 static void __secure ls1_start_fsm(void)
 112 {
 113         void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 114         void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
 115         struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 116         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 117
 118         /* Set HRSTCR */
 119         setbits_be32(&scfg->hrstcr, 0x80000000);
 120
 121         /* Place DDR controller in self refresh mode */
 122         setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
 123
 124         ls1_delay(2000);
 125
 126         /* Set EVT4_B to lock the signal MCKE down */
 127         out_be32(dcsr_epu_base + EPECR0, 0x0);
 128
 129         ls1_delay(2000);
 130
 131         out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
 132         out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
 133
 134         /* Enable all EPU Counters */
 135         setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
 136
 137         /* Enable SCU15 */
 138         setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
 139
 140         /* Enter WFI mode, and EPU FSM will start */
 141         __asm__ __volatile__ ("wfi" : : : "memory");
 142
 143         /* NEVER ENTER HERE */
 144         while (1)
 145                 ;
 146 }
 147
 148 static void __secure ls1_deep_sleep(u32 entry_point)
 149 {
 150         struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 151         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 152         struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
 153 #ifdef QIXIS_BASE
 154         u32 tmp;
 155         void *qixis_base = (void *)QIXIS_BASE;
 156 #endif
 157
 158         /* Enable cluster to enter the PCL10 state */
 159         out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
 160
 161         /* Save the first 128 bytes of DDR data */
 162         ls1_save_ddr_head();
 163
 164         /* Save the kernel resume entry */
 165         out_le32(&scfg->sparecr[3], entry_point);
 166
 167         /* Request to put cluster 0 in PCL10 state */
 168         setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
 169
 170         /* Setup the registers of the EPU FSM for deep sleep */
 171         ls1_fsm_setup();
 172
 173 #ifdef QIXIS_BASE
 174         /* Connect the EVENT button to IRQ in FPGA */
 175         tmp = in_8(qixis_base + QIXIS_CTL_SYS);
 176         tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
 177         tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
 178         out_8(qixis_base + QIXIS_CTL_SYS, tmp);
 179
 180         /* Enable deep sleep signals in FPGA */
 181         tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
 182         tmp |= QIXIS_PWR_CTL2_PCTL;
 183         out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
 184
 185         /* Pull down PCIe RST# */
 186         tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
 187         tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
 188         out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
 189 #endif
 190
 191         /* Enable Warm Device Reset */
 192         setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
 193         setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
 194
 195         ls1_deepsleep_irq_cfg();
 196
 197         psci_v7_flush_dcache_all();
 198
 199         ls1_start_fsm();
 200 }
 201
 202 #else
 203 static void __secure ls1_sleep(void)
 204 {
 205         struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 206         struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
 207
 208 #ifdef QIXIS_BASE
 209         u32 tmp;
 210         void *qixis_base = (void *)QIXIS_BASE;
 211
 212         /* Connect the EVENT button to IRQ in FPGA */
 213         tmp = in_8(qixis_base + QIXIS_CTL_SYS);
 214         tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
 215         tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
 216         out_8(qixis_base + QIXIS_CTL_SYS, tmp);
 217 #endif
 218
 219         /* Enable cluster to enter the PCL10 state */
 220         out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
 221
 222         setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
 223
 224         __asm__ __volatile__ ("wfi" : : : "memory");
 225 }
 226 #endif
 227
 228 void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
 229 {
 230 #ifdef CONFIG_LS1_DEEP_SLEEP
 231         ls1_deep_sleep(entry_point);
 232 #else
 233         ls1_sleep();
 234 #endif
 235 }