arch/arm/cpu/armv7/mx5/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <asm/arch/imx-regs.h>
  24 #include <generated/asm-offsets.h>
  25 #include <linux/linkage.h>
  26
  27 .section ".text.init", "x"
  28
  29 .macro init_arm_erratum
  30         /* ARM erratum ID #468414 */
  31         mrc 15, 0, r1, c1, c0, 1
  32         orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
  33         mcr 15, 0, r1, c1, c0, 1
  34 .endm
  35
  36 /*
  37  * L2CC Cache setup/invalidation/disable
  38  */
  39 .macro init_l2cc
  40         /* explicitly disable L2 cache */
  41         mrc 15, 0, r0, c1, c0, 1
  42         bic r0, r0, #0x2
  43         mcr 15, 0, r0, c1, c0, 1
  44
  45         /* reconfigure L2 cache aux control reg */
  46         ldr r0, =0xC0 |                 /* tag RAM */ \
  47                  0x4 |                  /* data RAM */ \
  48                  1 << 24 |              /* disable write allocate delay */ \
  49                  1 << 23 |              /* disable write allocate combine */ \
  50                  1 << 22                /* disable write allocate */
  51
  52 #if defined(CONFIG_MX51)
  53         ldr r3, [r4, #ROM_SI_REV]
  54         cmp r3, #0x10
  55
  56         /* disable write combine for TO 2 and lower revs */
  57         orrls r0, r0, #1 << 25
  58 #endif
  59
  60         mcr 15, 1, r0, c9, c0, 2
  61 .endm /* init_l2cc */
  62
  63 /* AIPS setup - Only setup MPROTx registers.
  64  * The PACR default values are good.*/
  65 .macro init_aips
  66         /*
  67          * Set all MPROTx to be non-bufferable, trusted for R/W,
  68          * not forced to user-mode.
  69          */
  70         ldr r0, =AIPS1_BASE_ADDR
  71         ldr r1, =0x77777777
  72         str r1, [r0, #0x0]
  73         str r1, [r0, #0x4]
  74         ldr r0, =AIPS2_BASE_ADDR
  75         str r1, [r0, #0x0]
  76         str r1, [r0, #0x4]
  77         /*
  78          * Clear the on and off peripheral modules Supervisor Protect bit
  79          * for SDMA to access them. Did not change the AIPS control registers
  80          * (offset 0x20) access type
  81          */
  82 .endm /* init_aips */
  83
  84 /* M4IF setup */
  85 .macro init_m4if
  86 #ifdef CONFIG_MX51
  87         /* VPU and IPU given higher priority (0x4)
  88          * IPU accesses with ID=0x1 given highest priority (=0xA)
  89          */
  90         ldr r0, =M4IF_BASE_ADDR
  91
  92         ldr r1, =0x00000203
  93         str r1, [r0, #0x40]
  94
  95         str r4, [r0, #0x44]
  96
  97         ldr r1, =0x00120125
  98         str r1, [r0, #0x9C]
  99
 100         ldr r1, =0x001901A3
 101         str r1, [r0, #0x48]
 102
 103 #endif
 104 .endm /* init_m4if */
 105
 106 .macro setup_pll pll, freq
 107         ldr r0, =\pll
 108         adr r2, W_DP_\freq
 109         bl setup_pll_func
 110 .endm
 111
 112 #define W_DP_OP         0
 113 #define W_DP_MFD        4
 114 #define W_DP_MFN        8
 115
 116 setup_pll_func:
 117         ldr r1, =0x00001232
 118         str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 119         mov r1, #0x2
 120         str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 121
 122         ldr r1, [r2, #W_DP_OP]
 123         str r1, [r0, #PLL_DP_OP]
 124         str r1, [r0, #PLL_DP_HFS_OP]
 125
 126         ldr r1, [r2, #W_DP_MFD]
 127         str r1, [r0, #PLL_DP_MFD]
 128         str r1, [r0, #PLL_DP_HFS_MFD]
 129
 130         ldr r1, [r2, #W_DP_MFN]
 131         str r1, [r0, #PLL_DP_MFN]
 132         str r1, [r0, #PLL_DP_HFS_MFN]
 133
 134         ldr r1, =0x00001232
 135         str r1, [r0, #PLL_DP_CTL]
 136 1:      ldr r1, [r0, #PLL_DP_CTL]
 137         ands r1, r1, #0x1
 138         beq 1b
 139
 140         /* r10 saved upper lr */
 141         mov pc, lr
 142
 143 .macro setup_pll_errata pll, freq
 144         ldr r2, =\pll
 145         str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 146         ldr r1, =0x00001236
 147         str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 148 1:      ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
 149         ands r1, r1, #0x1
 150         beq 1b
 151
 152         ldr r5, \freq
 153         str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
 154         str r5, [r2, #PLL_DP_HFS_MFN]
 155
 156         mov r1, #0x1
 157         str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
 158
 159 2:      ldr r1, [r2, #PLL_DP_CONFIG]
 160         tst r1, #1
 161         bne 2b
 162
 163         ldr r1, =100                 /* Wait at least 4 us */
 164 3:      subs r1, r1, #1
 165         bge 3b
 166
 167         mov r1, #0x2
 168         str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 169 .endm
 170
 171 .macro init_clock
 172 #if defined (CONFIG_MX51)
 173         ldr r0, =CCM_BASE_ADDR
 174
 175         /* Gate of clocks to the peripherals first */
 176         ldr r1, =0x3FFFFFFF
 177         str r1, [r0, #CLKCTL_CCGR0]
 178         str r4, [r0, #CLKCTL_CCGR1]
 179         str r4, [r0, #CLKCTL_CCGR2]
 180         str r4, [r0, #CLKCTL_CCGR3]
 181
 182         ldr r1, =0x00030000
 183         str r1, [r0, #CLKCTL_CCGR4]
 184         ldr r1, =0x00FFF030
 185         str r1, [r0, #CLKCTL_CCGR5]
 186         ldr r1, =0x00000300
 187         str r1, [r0, #CLKCTL_CCGR6]
 188
 189         /* Disable IPU and HSC dividers */
 190         mov r1, #0x60000
 191         str r1, [r0, #CLKCTL_CCDR]
 192
 193         /* Make sure to switch the DDR away from PLL 1 */
 194         ldr r1, =0x19239145
 195         str r1, [r0, #CLKCTL_CBCDR]
 196         /* make sure divider effective */
 197 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 198         cmp r1, #0x0
 199         bne 1b
 200
 201         /* Switch ARM to step clock */
 202         mov r1, #0x4
 203         str r1, [r0, #CLKCTL_CCSR]
 204
 205 #if defined(CONFIG_MX51_PLL_ERRATA)
 206         setup_pll PLL1_BASE_ADDR, 864
 207         setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
 208 #else
 209         setup_pll PLL1_BASE_ADDR, 800
 210 #endif
 211
 212         setup_pll PLL3_BASE_ADDR, 665
 213
 214         /* Switch peripheral to PLL 3 */
 215         ldr r0, =CCM_BASE_ADDR
 216         ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
 217         str r1, [r0, #CLKCTL_CBCMR]
 218         ldr r1, =0x13239145
 219         str r1, [r0, #CLKCTL_CBCDR]
 220         setup_pll PLL2_BASE_ADDR, 665
 221
 222         /* Switch peripheral to PLL2 */
 223         ldr r0, =CCM_BASE_ADDR
 224         ldr r1, =0x19239145
 225         str r1, [r0, #CLKCTL_CBCDR]
 226         ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
 227         str r1, [r0, #CLKCTL_CBCMR]
 228
 229         setup_pll PLL3_BASE_ADDR, 216
 230
 231         /* Set the platform clock dividers */
 232         ldr r0, =ARM_BASE_ADDR
 233         ldr r1, =0x00000725
 234         str r1, [r0, #0x14]
 235
 236         ldr r0, =CCM_BASE_ADDR
 237
 238         /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 239         ldr r3, [r4, #ROM_SI_REV]
 240         cmp r3, #0x10
 241         movls r1, #0x1
 242         movhi r1, #0
 243
 244         str r1, [r0, #CLKCTL_CACRR]
 245
 246         /* Switch ARM back to PLL 1 */
 247         str r4, [r0, #CLKCTL_CCSR]
 248
 249         /* setup the rest */
 250         /* Use lp_apm (24MHz) source for perclk */
 251         ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
 252         str r1, [r0, #CLKCTL_CBCMR]
 253         /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 254         ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 255         str r1, [r0, #CLKCTL_CBCDR]
 256
 257         /* Restore the default values in the Gate registers */
 258         ldr r1, =0xFFFFFFFF
 259         str r1, [r0, #CLKCTL_CCGR0]
 260         str r1, [r0, #CLKCTL_CCGR1]
 261         str r1, [r0, #CLKCTL_CCGR2]
 262         str r1, [r0, #CLKCTL_CCGR3]
 263         str r1, [r0, #CLKCTL_CCGR4]
 264         str r1, [r0, #CLKCTL_CCGR5]
 265         str r1, [r0, #CLKCTL_CCGR6]
 266
 267         /* Use PLL 2 for UART's, get 66.5MHz from it */
 268         ldr r1, =0xA5A2A020
 269         str r1, [r0, #CLKCTL_CSCMR1]
 270         ldr r1, =0x00C30321
 271         str r1, [r0, #CLKCTL_CSCDR1]
 272         /* make sure divider effective */
 273 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 274         cmp r1, #0x0
 275         bne 1b
 276
 277         str r4, [r0, #CLKCTL_CCDR]
 278
 279         /* for cko - for ARM div by 8 */
 280         mov r1, #0x000A0000
 281         add r1, r1, #0x00000F0
 282         str r1, [r0, #CLKCTL_CCOSR]
 283 #else   /* CONFIG_MX53 */
 284         ldr r0, =CCM_BASE_ADDR
 285
 286         /* Gate of clocks to the peripherals first */
 287         ldr r1, =0x3FFFFFFF
 288         str r1, [r0, #CLKCTL_CCGR0]
 289         str r4, [r0, #CLKCTL_CCGR1]
 290         str r4, [r0, #CLKCTL_CCGR2]
 291         str r4, [r0, #CLKCTL_CCGR3]
 292         str r4, [r0, #CLKCTL_CCGR7]
 293         ldr r1, =0x00030000
 294         str r1, [r0, #CLKCTL_CCGR4]
 295         ldr r1, =0x00FFF030
 296         str r1, [r0, #CLKCTL_CCGR5]
 297         ldr r1, =0x0F00030F
 298         str r1, [r0, #CLKCTL_CCGR6]
 299
 300         /* Switch ARM to step clock */
 301         mov r1, #0x4
 302         str r1, [r0, #CLKCTL_CCSR]
 303
 304         setup_pll PLL1_BASE_ADDR, 800
 305
 306         setup_pll PLL3_BASE_ADDR, 400
 307
 308         /* Switch peripheral to PLL3 */
 309         ldr r0, =CCM_BASE_ADDR
 310         ldr r1, =0x00015154
 311         str r1, [r0, #CLKCTL_CBCMR]
 312         ldr r1, =0x02888945
 313         orr r1, r1, #(1 << 16)
 314         str r1, [r0, #CLKCTL_CBCDR]
 315         /* make sure change is effective */
 316 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 317         cmp r1, #0x0
 318         bne 1b
 319
 320         setup_pll PLL2_BASE_ADDR, 400
 321
 322         /* Switch peripheral to PLL2 */
 323         ldr r0, =CCM_BASE_ADDR
 324         ldr r1, =0x00808145
 325         orr r1, r1, #(2 << 10)
 326         orr r1, r1, #(0 << 16)
 327         orr r1, r1, #(1 << 19)
 328         str r1, [r0, #CLKCTL_CBCDR]
 329
 330         ldr r1, =0x00016154
 331         str r1, [r0, #CLKCTL_CBCMR]
 332
 333         /*change uart clk parent to pll2*/
 334         ldr r1, [r0, #CLKCTL_CSCMR1]
 335         and r1, r1, #0xfcffffff
 336         orr r1, r1, #0x01000000
 337         str r1, [r0, #CLKCTL_CSCMR1]
 338
 339         /* make sure change is effective */
 340 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 341         cmp r1, #0x0
 342         bne 1b
 343
 344         setup_pll PLL3_BASE_ADDR, 216
 345
 346         setup_pll PLL4_BASE_ADDR, 455
 347
 348         /* Set the platform clock dividers */
 349         ldr r0, =ARM_BASE_ADDR
 350         ldr r1, =0x00000124
 351         str r1, [r0, #0x14]
 352
 353         ldr r0, =CCM_BASE_ADDR
 354         mov r1, #0
 355         str r1, [r0, #CLKCTL_CACRR]
 356
 357         /* Switch ARM back to PLL 1. */
 358         mov r1, #0x0
 359         str r1, [r0, #CLKCTL_CCSR]
 360
 361         /* make uart div=6 */
 362         ldr r1, [r0, #CLKCTL_CSCDR1]
 363         and r1, r1, #0xffffffc0
 364         orr r1, r1, #0x0a
 365         str r1, [r0, #CLKCTL_CSCDR1]
 366
 367         /* Restore the default values in the Gate registers */
 368         ldr r1, =0xFFFFFFFF
 369         str r1, [r0, #CLKCTL_CCGR0]
 370         str r1, [r0, #CLKCTL_CCGR1]
 371         str r1, [r0, #CLKCTL_CCGR2]
 372         str r1, [r0, #CLKCTL_CCGR3]
 373         str r1, [r0, #CLKCTL_CCGR4]
 374         str r1, [r0, #CLKCTL_CCGR5]
 375         str r1, [r0, #CLKCTL_CCGR6]
 376         str r1, [r0, #CLKCTL_CCGR7]
 377
 378         mov r1, #0x00000
 379         str r1, [r0, #CLKCTL_CCDR]
 380
 381         /* for cko - for ARM div by 8 */
 382         mov r1, #0x000A0000
 383         add r1, r1, #0x00000F0
 384         str r1, [r0, #CLKCTL_CCOSR]
 385
 386 #endif  /* CONFIG_MX53 */
 387 .endm
 388
 389 .macro setup_wdog
 390         ldr r0, =WDOG1_BASE_ADDR
 391         mov r1, #0x30
 392         strh r1, [r0]
 393 .endm
 394
 395 ENTRY(lowlevel_init)
 396         mov r10, lr
 397         mov r4, #0      /* Fix R4 to 0 */
 398
 399 #if defined(CONFIG_SYS_MAIN_PWR_ON)
 400         ldr r0, =GPIO1_BASE_ADDR
 401         ldr r1, [r0, #0x0]
 402         orr r1, r1, #1 << 23
 403         str r1, [r0, #0x0]
 404         ldr r1, [r0, #0x4]
 405         orr r1, r1, #1 << 23
 406         str r1, [r0, #0x4]
 407 #endif
 408
 409         init_arm_erratum
 410
 411         init_l2cc
 412
 413         init_aips
 414
 415         init_m4if
 416
 417         init_clock
 418
 419         mov pc, r10
 420 ENDPROC(lowlevel_init)
 421
 422 /* Board level setting value */
 423 #if defined(CONFIG_MX51_PLL_ERRATA)
 424 W_DP_864:               .word DP_OP_864
 425                         .word DP_MFD_864
 426                         .word DP_MFN_864
 427 W_DP_MFN_800_DIT:       .word DP_MFN_800_DIT
 428 #else
 429 W_DP_800:               .word DP_OP_800
 430                         .word DP_MFD_800
 431                         .word DP_MFN_800
 432 #endif
 433 #if defined(CONFIG_MX51)
 434 W_DP_665:               .word DP_OP_665
 435                         .word DP_MFD_665
 436                         .word DP_MFN_665
 437 #endif
 438 W_DP_216:               .word DP_OP_216
 439                         .word DP_MFD_216
 440                         .word DP_MFN_216
 441 W_DP_400:               .word DP_OP_400
 442                         .word DP_MFD_400
 443                         .word DP_MFN_400
 444 W_DP_455:               .word DP_OP_455
 445                         .word DP_MFD_455
 446                         .word DP_MFN_455