arch/arm/cpu/armv7/mx5/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <generated/asm-offsets.h>
  12 #include <linux/linkage.h>
  13
  14 .section ".text.init", "x"
  15
  16 .macro init_arm_erratum
  17         /* ARM erratum ID #468414 */
  18         mrc 15, 0, r1, c1, c0, 1
  19         orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
  20         mcr 15, 0, r1, c1, c0, 1
  21 .endm
  22
  23 /*
  24  * L2CC Cache setup/invalidation/disable
  25  */
  26 .macro init_l2cc
  27         /* explicitly disable L2 cache */
  28         mrc 15, 0, r0, c1, c0, 1
  29         bic r0, r0, #0x2
  30         mcr 15, 0, r0, c1, c0, 1
  31
  32         /* reconfigure L2 cache aux control reg */
  33         ldr r0, =0xC0 |                 /* tag RAM */ \
  34                  0x4 |                  /* data RAM */ \
  35                  1 << 24 |              /* disable write allocate delay */ \
  36                  1 << 23 |              /* disable write allocate combine */ \
  37                  1 << 22                /* disable write allocate */
  38
  39 #if defined(CONFIG_MX51)
  40         ldr r3, [r4, #ROM_SI_REV]
  41         cmp r3, #0x10
  42
  43         /* disable write combine for TO 2 and lower revs */
  44         orrls r0, r0, #1 << 25
  45 #endif
  46
  47         mcr 15, 1, r0, c9, c0, 2
  48 .endm /* init_l2cc */
  49
  50 /* AIPS setup - Only setup MPROTx registers.
  51  * The PACR default values are good.*/
  52 .macro init_aips
  53         /*
  54          * Set all MPROTx to be non-bufferable, trusted for R/W,
  55          * not forced to user-mode.
  56          */
  57         ldr r0, =AIPS1_BASE_ADDR
  58         ldr r1, =0x77777777
  59         str r1, [r0, #0x0]
  60         str r1, [r0, #0x4]
  61         ldr r0, =AIPS2_BASE_ADDR
  62         str r1, [r0, #0x0]
  63         str r1, [r0, #0x4]
  64         /*
  65          * Clear the on and off peripheral modules Supervisor Protect bit
  66          * for SDMA to access them. Did not change the AIPS control registers
  67          * (offset 0x20) access type
  68          */
  69 .endm /* init_aips */
  70
  71 /* M4IF setup */
  72 .macro init_m4if
  73 #ifdef CONFIG_MX51
  74         /* VPU and IPU given higher priority (0x4)
  75          * IPU accesses with ID=0x1 given highest priority (=0xA)
  76          */
  77         ldr r0, =M4IF_BASE_ADDR
  78
  79         ldr r1, =0x00000203
  80         str r1, [r0, #0x40]
  81
  82         str r4, [r0, #0x44]
  83
  84         ldr r1, =0x00120125
  85         str r1, [r0, #0x9C]
  86
  87         ldr r1, =0x001901A3
  88         str r1, [r0, #0x48]
  89
  90 #endif
  91 .endm /* init_m4if */
  92
  93 .macro setup_pll pll, freq
  94         ldr r0, =\pll
  95         adr r2, W_DP_\freq
  96         bl setup_pll_func
  97 .endm
  98
  99 #define W_DP_OP         0
 100 #define W_DP_MFD        4
 101 #define W_DP_MFN        8
 102
 103 setup_pll_func:
 104         ldr r1, =0x00001232
 105         str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 106         mov r1, #0x2
 107         str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 108
 109         ldr r1, [r2, #W_DP_OP]
 110         str r1, [r0, #PLL_DP_OP]
 111         str r1, [r0, #PLL_DP_HFS_OP]
 112
 113         ldr r1, [r2, #W_DP_MFD]
 114         str r1, [r0, #PLL_DP_MFD]
 115         str r1, [r0, #PLL_DP_HFS_MFD]
 116
 117         ldr r1, [r2, #W_DP_MFN]
 118         str r1, [r0, #PLL_DP_MFN]
 119         str r1, [r0, #PLL_DP_HFS_MFN]
 120
 121         ldr r1, =0x00001232
 122         str r1, [r0, #PLL_DP_CTL]
 123 1:      ldr r1, [r0, #PLL_DP_CTL]
 124         ands r1, r1, #0x1
 125         beq 1b
 126
 127         /* r10 saved upper lr */
 128         mov pc, lr
 129
 130 .macro setup_pll_errata pll, freq
 131         ldr r2, =\pll
 132         str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 133         ldr r1, =0x00001236
 134         str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 135 1:      ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
 136         ands r1, r1, #0x1
 137         beq 1b
 138
 139         ldr r5, \freq
 140         str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
 141         str r5, [r2, #PLL_DP_HFS_MFN]
 142
 143         mov r1, #0x1
 144         str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
 145
 146 2:      ldr r1, [r2, #PLL_DP_CONFIG]
 147         tst r1, #1
 148         bne 2b
 149
 150         ldr r1, =100                 /* Wait at least 4 us */
 151 3:      subs r1, r1, #1
 152         bge 3b
 153
 154         mov r1, #0x2
 155         str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 156 .endm
 157
 158 .macro init_clock
 159 #if defined (CONFIG_MX51)
 160         ldr r0, =CCM_BASE_ADDR
 161
 162         /* Gate of clocks to the peripherals first */
 163         ldr r1, =0x3FFFFFFF
 164         str r1, [r0, #CLKCTL_CCGR0]
 165         str r4, [r0, #CLKCTL_CCGR1]
 166         str r4, [r0, #CLKCTL_CCGR2]
 167         str r4, [r0, #CLKCTL_CCGR3]
 168
 169         ldr r1, =0x00030000
 170         str r1, [r0, #CLKCTL_CCGR4]
 171         ldr r1, =0x00FFF030
 172         str r1, [r0, #CLKCTL_CCGR5]
 173         ldr r1, =0x00000300
 174         str r1, [r0, #CLKCTL_CCGR6]
 175
 176         /* Disable IPU and HSC dividers */
 177         mov r1, #0x60000
 178         str r1, [r0, #CLKCTL_CCDR]
 179
 180         /* Make sure to switch the DDR away from PLL 1 */
 181         ldr r1, =0x19239145
 182         str r1, [r0, #CLKCTL_CBCDR]
 183         /* make sure divider effective */
 184 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 185         cmp r1, #0x0
 186         bne 1b
 187
 188         /* Switch ARM to step clock */
 189         mov r1, #0x4
 190         str r1, [r0, #CLKCTL_CCSR]
 191
 192 #if defined(CONFIG_MX51_PLL_ERRATA)
 193         setup_pll PLL1_BASE_ADDR, 864
 194         setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
 195 #else
 196         setup_pll PLL1_BASE_ADDR, 800
 197 #endif
 198
 199         setup_pll PLL3_BASE_ADDR, 665
 200
 201         /* Switch peripheral to PLL 3 */
 202         ldr r0, =CCM_BASE_ADDR
 203         ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
 204         str r1, [r0, #CLKCTL_CBCMR]
 205         ldr r1, =0x13239145
 206         str r1, [r0, #CLKCTL_CBCDR]
 207         setup_pll PLL2_BASE_ADDR, 665
 208
 209         /* Switch peripheral to PLL2 */
 210         ldr r0, =CCM_BASE_ADDR
 211         ldr r1, =0x19239145
 212         str r1, [r0, #CLKCTL_CBCDR]
 213         ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
 214         str r1, [r0, #CLKCTL_CBCMR]
 215
 216         setup_pll PLL3_BASE_ADDR, 216
 217
 218         /* Set the platform clock dividers */
 219         ldr r0, =ARM_BASE_ADDR
 220         ldr r1, =0x00000725
 221         str r1, [r0, #0x14]
 222
 223         ldr r0, =CCM_BASE_ADDR
 224
 225         /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 226         ldr r3, [r4, #ROM_SI_REV]
 227         cmp r3, #0x10
 228         movls r1, #0x1
 229         movhi r1, #0
 230
 231         str r1, [r0, #CLKCTL_CACRR]
 232
 233         /* Switch ARM back to PLL 1 */
 234         str r4, [r0, #CLKCTL_CCSR]
 235
 236         /* setup the rest */
 237         /* Use lp_apm (24MHz) source for perclk */
 238         ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
 239         str r1, [r0, #CLKCTL_CBCMR]
 240         /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 241         ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 242         str r1, [r0, #CLKCTL_CBCDR]
 243
 244         /* Restore the default values in the Gate registers */
 245         ldr r1, =0xFFFFFFFF
 246         str r1, [r0, #CLKCTL_CCGR0]
 247         str r1, [r0, #CLKCTL_CCGR1]
 248         str r1, [r0, #CLKCTL_CCGR2]
 249         str r1, [r0, #CLKCTL_CCGR3]
 250         str r1, [r0, #CLKCTL_CCGR4]
 251         str r1, [r0, #CLKCTL_CCGR5]
 252         str r1, [r0, #CLKCTL_CCGR6]
 253
 254         /* Use PLL 2 for UART's, get 66.5MHz from it */
 255         ldr r1, =0xA5A2A020
 256         str r1, [r0, #CLKCTL_CSCMR1]
 257         ldr r1, =0x00C30321
 258         str r1, [r0, #CLKCTL_CSCDR1]
 259         /* make sure divider effective */
 260 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 261         cmp r1, #0x0
 262         bne 1b
 263
 264         str r4, [r0, #CLKCTL_CCDR]
 265
 266         /* for cko - for ARM div by 8 */
 267         mov r1, #0x000A0000
 268         add r1, r1, #0x00000F0
 269         str r1, [r0, #CLKCTL_CCOSR]
 270 #else   /* CONFIG_MX53 */
 271         ldr r0, =CCM_BASE_ADDR
 272
 273         /* Gate of clocks to the peripherals first */
 274         ldr r1, =0x3FFFFFFF
 275         str r1, [r0, #CLKCTL_CCGR0]
 276         str r4, [r0, #CLKCTL_CCGR1]
 277         str r4, [r0, #CLKCTL_CCGR2]
 278         str r4, [r0, #CLKCTL_CCGR3]
 279         str r4, [r0, #CLKCTL_CCGR7]
 280         ldr r1, =0x00030000
 281         str r1, [r0, #CLKCTL_CCGR4]
 282         ldr r1, =0x00FFF030
 283         str r1, [r0, #CLKCTL_CCGR5]
 284         ldr r1, =0x0F00030F
 285         str r1, [r0, #CLKCTL_CCGR6]
 286
 287         /* Switch ARM to step clock */
 288         mov r1, #0x4
 289         str r1, [r0, #CLKCTL_CCSR]
 290
 291         setup_pll PLL1_BASE_ADDR, 800
 292
 293         setup_pll PLL3_BASE_ADDR, 400
 294
 295         /* Switch peripheral to PLL3 */
 296         ldr r0, =CCM_BASE_ADDR
 297         ldr r1, =0x00015154
 298         str r1, [r0, #CLKCTL_CBCMR]
 299         ldr r1, =0x02898945
 300         str r1, [r0, #CLKCTL_CBCDR]
 301         /* make sure change is effective */
 302 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 303         cmp r1, #0x0
 304         bne 1b
 305
 306         setup_pll PLL2_BASE_ADDR, 400
 307
 308         /* Switch peripheral to PLL2 */
 309         ldr r0, =CCM_BASE_ADDR
 310         ldr r1, =0x00888945
 311         str r1, [r0, #CLKCTL_CBCDR]
 312
 313         ldr r1, =0x00016154
 314         str r1, [r0, #CLKCTL_CBCMR]
 315
 316         /*change uart clk parent to pll2*/
 317         ldr r1, [r0, #CLKCTL_CSCMR1]
 318         and r1, r1, #0xfcffffff
 319         orr r1, r1, #0x01000000
 320         str r1, [r0, #CLKCTL_CSCMR1]
 321
 322         /* make sure change is effective */
 323 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 324         cmp r1, #0x0
 325         bne 1b
 326
 327         setup_pll PLL3_BASE_ADDR, 216
 328
 329         setup_pll PLL4_BASE_ADDR, 455
 330
 331         /* Set the platform clock dividers */
 332         ldr r0, =ARM_BASE_ADDR
 333         ldr r1, =0x00000124
 334         str r1, [r0, #0x14]
 335
 336         ldr r0, =CCM_BASE_ADDR
 337         mov r1, #0
 338         str r1, [r0, #CLKCTL_CACRR]
 339
 340         /* Switch ARM back to PLL 1. */
 341         mov r1, #0x0
 342         str r1, [r0, #CLKCTL_CCSR]
 343
 344         /* make uart div=6 */
 345         ldr r1, [r0, #CLKCTL_CSCDR1]
 346         and r1, r1, #0xffffffc0
 347         orr r1, r1, #0x0a
 348         str r1, [r0, #CLKCTL_CSCDR1]
 349
 350         /* Restore the default values in the Gate registers */
 351         ldr r1, =0xFFFFFFFF
 352         str r1, [r0, #CLKCTL_CCGR0]
 353         str r1, [r0, #CLKCTL_CCGR1]
 354         str r1, [r0, #CLKCTL_CCGR2]
 355         str r1, [r0, #CLKCTL_CCGR3]
 356         str r1, [r0, #CLKCTL_CCGR4]
 357         str r1, [r0, #CLKCTL_CCGR5]
 358         str r1, [r0, #CLKCTL_CCGR6]
 359         str r1, [r0, #CLKCTL_CCGR7]
 360
 361         mov r1, #0x00000
 362         str r1, [r0, #CLKCTL_CCDR]
 363
 364         /* for cko - for ARM div by 8 */
 365         mov r1, #0x000A0000
 366         add r1, r1, #0x00000F0
 367         str r1, [r0, #CLKCTL_CCOSR]
 368
 369 #endif  /* CONFIG_MX53 */
 370 .endm
 371
 372 .macro setup_wdog
 373         ldr r0, =WDOG1_BASE_ADDR
 374         mov r1, #0x30
 375         strh r1, [r0]
 376 .endm
 377
 378 ENTRY(lowlevel_init)
 379         mov r10, lr
 380         mov r4, #0      /* Fix R4 to 0 */
 381
 382 #if defined(CONFIG_SYS_MAIN_PWR_ON)
 383         ldr r0, =GPIO1_BASE_ADDR
 384         ldr r1, [r0, #0x0]
 385         orr r1, r1, #1 << 23
 386         str r1, [r0, #0x0]
 387         ldr r1, [r0, #0x4]
 388         orr r1, r1, #1 << 23
 389         str r1, [r0, #0x4]
 390 #endif
 391
 392         init_arm_erratum
 393
 394         init_l2cc
 395
 396         init_aips
 397
 398         init_m4if
 399
 400         init_clock
 401
 402         mov pc, r10
 403 ENDPROC(lowlevel_init)
 404
 405 /* Board level setting value */
 406 #if defined(CONFIG_MX51_PLL_ERRATA)
 407 W_DP_864:               .word DP_OP_864
 408                         .word DP_MFD_864
 409                         .word DP_MFN_864
 410 W_DP_MFN_800_DIT:       .word DP_MFN_800_DIT
 411 #else
 412 W_DP_800:               .word DP_OP_800
 413                         .word DP_MFD_800
 414                         .word DP_MFN_800
 415 #endif
 416 #if defined(CONFIG_MX51)
 417 W_DP_665:               .word DP_OP_665
 418                         .word DP_MFD_665
 419                         .word DP_MFN_665
 420 #endif
 421 W_DP_216:               .word DP_OP_216
 422                         .word DP_MFD_216
 423                         .word DP_MFN_216
 424 W_DP_400:               .word DP_OP_400
 425                         .word DP_MFD_400
 426                         .word DP_MFN_400
 427 W_DP_455:               .word DP_OP_455
 428                         .word DP_MFD_455
 429                         .word DP_MFN_455