arch/arm/cpu/armv7/mx5/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <asm/arch/imx-regs.h>
  24 #include <generated/asm-offsets.h>
  25 #include <linux/linkage.h>
  26
  27 /*
  28  * L2CC Cache setup/invalidation/disable
  29  */
  30 .macro init_l2cc
  31         /* explicitly disable L2 cache */
  32         mrc 15, 0, r0, c1, c0, 1
  33         bic r0, r0, #0x2
  34         mcr 15, 0, r0, c1, c0, 1
  35
  36         /* reconfigure L2 cache aux control reg */
  37         mov r0, #0xC0                   /* tag RAM */
  38         add r0, r0, #0x4                /* data RAM */
  39         orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  40         orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  41         orr r0, r0, #(1 << 22)          /* disable write allocate */
  42
  43 #if defined(CONFIG_MX51)
  44         ldr r1, =0x0
  45         ldr r3, [r1, #ROM_SI_REV]
  46         cmp r3, #0x10
  47
  48         /* disable write combine for TO 2 and lower revs */
  49         orrls r0, r0, #(1 << 25)
  50 #endif
  51
  52         mcr 15, 1, r0, c9, c0, 2
  53 .endm /* init_l2cc */
  54
  55 /* AIPS setup - Only setup MPROTx registers.
  56  * The PACR default values are good.*/
  57 .macro init_aips
  58         /*
  59          * Set all MPROTx to be non-bufferable, trusted for R/W,
  60          * not forced to user-mode.
  61          */
  62         ldr r0, =AIPS1_BASE_ADDR
  63         ldr r1, =0x77777777
  64         str r1, [r0, #0x0]
  65         str r1, [r0, #0x4]
  66         ldr r0, =AIPS2_BASE_ADDR
  67         str r1, [r0, #0x0]
  68         str r1, [r0, #0x4]
  69         /*
  70          * Clear the on and off peripheral modules Supervisor Protect bit
  71          * for SDMA to access them. Did not change the AIPS control registers
  72          * (offset 0x20) access type
  73          */
  74 .endm /* init_aips */
  75
  76 /* M4IF setup */
  77 .macro init_m4if
  78 #ifdef CONFIG_MX51
  79         /* VPU and IPU given higher priority (0x4)
  80          * IPU accesses with ID=0x1 given highest priority (=0xA)
  81          */
  82         ldr r0, =M4IF_BASE_ADDR
  83
  84         ldr r1, =0x00000203
  85         str r1, [r0, #0x40]
  86
  87         ldr r1, =0x0
  88         str r1, [r0, #0x44]
  89
  90         ldr r1, =0x00120125
  91         str r1, [r0, #0x9C]
  92
  93         ldr r1, =0x001901A3
  94         str r1, [r0, #0x48]
  95
  96 #endif
  97 .endm /* init_m4if */
  98
  99 .macro setup_pll pll, freq
 100         ldr r0, =\pll
 101         ldr r1, =0x00001232
 102         str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 103         mov r1, #0x2
 104         str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 105
 106         ldr r1, W_DP_OP_\freq
 107         str r1, [r0, #PLL_DP_OP]
 108         str r1, [r0, #PLL_DP_HFS_OP]
 109
 110         ldr r1, W_DP_MFD_\freq
 111         str r1, [r0, #PLL_DP_MFD]
 112         str r1, [r0, #PLL_DP_HFS_MFD]
 113
 114         ldr r1,  W_DP_MFN_\freq
 115         str r1, [r0, #PLL_DP_MFN]
 116         str r1, [r0, #PLL_DP_HFS_MFN]
 117
 118         ldr r1, =0x00001232
 119         str r1, [r0, #PLL_DP_CTL]
 120 1:      ldr r1, [r0, #PLL_DP_CTL]
 121         ands r1, r1, #0x1
 122         beq 1b
 123 .endm
 124
 125 .macro setup_pll_errata pll, freq
 126         ldr r2, =\pll
 127         mov r1, #0x0
 128         str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 129         ldr r1, =0x00001236
 130         str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 131 1:      ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
 132         ands r1, r1, #0x1
 133         beq 1b
 134
 135         ldr r5, \freq
 136         str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
 137         str r5, [r2, #PLL_DP_HFS_MFN]
 138
 139         mov r1, #0x1
 140         str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
 141
 142 2:      ldr r1, [r2, #PLL_DP_CONFIG]
 143         tst r1, #1
 144         bne 2b
 145
 146         ldr r1, =100                 /* Wait at least 4 us */
 147 3:      subs r1, r1, #1
 148         bge 3b
 149
 150         mov r1, #0x2
 151         str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 152 .endm
 153
 154 .macro init_clock
 155         ldr r0, =CCM_BASE_ADDR
 156
 157 #if defined(CONFIG_MX51)
 158         /* Gate of clocks to the peripherals first */
 159         ldr r1, =0x3FFFFFFF
 160         str r1, [r0, #CLKCTL_CCGR0]
 161         ldr r1, =0x0
 162         str r1, [r0, #CLKCTL_CCGR1]
 163         str r1, [r0, #CLKCTL_CCGR2]
 164         str r1, [r0, #CLKCTL_CCGR3]
 165
 166         ldr r1, =0x00030000
 167         str r1, [r0, #CLKCTL_CCGR4]
 168         ldr r1, =0x00FFF030
 169         str r1, [r0, #CLKCTL_CCGR5]
 170         ldr r1, =0x00000300
 171         str r1, [r0, #CLKCTL_CCGR6]
 172
 173         /* Disable IPU and HSC dividers */
 174         mov r1, #0x60000
 175         str r1, [r0, #CLKCTL_CCDR]
 176
 177         /* Make sure to switch the DDR away from PLL 1 */
 178         ldr r1, =0x19239145
 179         str r1, [r0, #CLKCTL_CBCDR]
 180         /* make sure divider effective */
 181 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 182         cmp r1, #0x0
 183         bne 1b
 184 #else
 185         ldr r1, =0x3FFFFFFF
 186         str r1, [r0, #CLKCTL_CCGR0]
 187         ldr r1, =0x0
 188         str r1, [r0, #CLKCTL_CCGR1]
 189         str r1, [r0, #CLKCTL_CCGR2]
 190         str r1, [r0, #CLKCTL_CCGR3]
 191         str r1, [r0, #CLKCTL_CCGR7]
 192
 193         ldr r1, =0x00030000
 194         str r1, [r0, #CLKCTL_CCGR4]
 195         ldr r1, =0x00FFF030
 196         str r1, [r0, #CLKCTL_CCGR5]
 197         ldr r1, =0x0F00030F
 198         str r1, [r0, #CLKCTL_CCGR6]
 199 #endif
 200
 201         /* Switch ARM to step clock */
 202         mov r1, #0x4
 203         str r1, [r0, #CLKCTL_CCSR]
 204
 205 #if defined(CONFIG_MX51_PLL_ERRATA)
 206         setup_pll PLL1_BASE_ADDR, 864
 207         setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
 208 #else
 209         setup_pll PLL1_BASE_ADDR, 800
 210 #endif
 211
 212 #if defined(CONFIG_MX51)
 213         setup_pll PLL3_BASE_ADDR, 665
 214
 215         /* Switch peripheral to PLL 3 */
 216         ldr r0, =CCM_BASE_ADDR
 217         ldr r1, =0x000010C0
 218         orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 219         str r1, [r0, #CLKCTL_CBCMR]
 220         ldr r1, =0x13239145
 221         str r1, [r0, #CLKCTL_CBCDR]
 222         setup_pll PLL2_BASE_ADDR, 665
 223
 224         /* Switch peripheral to PLL2 */
 225         ldr r0, =CCM_BASE_ADDR
 226         ldr r1, =0x19239145
 227         str r1, [r0, #CLKCTL_CBCDR]
 228         ldr r1, =0x000020C0
 229         orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 230         str r1, [r0, #CLKCTL_CBCMR]
 231 #endif
 232         setup_pll PLL3_BASE_ADDR, 216
 233
 234         /* Set the platform clock dividers */
 235         ldr r0, =ARM_BASE_ADDR
 236         ldr r1, =0x00000725
 237         str r1, [r0, #0x14]
 238
 239         ldr r0, =CCM_BASE_ADDR
 240
 241 #if defined(CONFIG_MX51)
 242         /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 243         ldr r1, =0x0
 244         ldr r3, [r1, #ROM_SI_REV]
 245         cmp r3, #0x10
 246         movls r1, #0x1
 247         movhi r1, #0
 248 #else
 249         mov r1, #0
 250
 251 #endif
 252         str r1, [r0, #CLKCTL_CACRR]
 253         /* Switch ARM back to PLL 1 */
 254         mov r1, #0
 255         str r1, [r0, #CLKCTL_CCSR]
 256
 257 #if defined(CONFIG_MX51)
 258         /* setup the rest */
 259         /* Use lp_apm (24MHz) source for perclk */
 260         ldr r1, =0x000020C2
 261         orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 262         str r1, [r0, #CLKCTL_CBCMR]
 263         /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 264         ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 265         str r1, [r0, #CLKCTL_CBCDR]
 266 #endif
 267
 268         /* Restore the default values in the Gate registers */
 269         ldr r1, =0xFFFFFFFF
 270         str r1, [r0, #CLKCTL_CCGR0]
 271         str r1, [r0, #CLKCTL_CCGR1]
 272         str r1, [r0, #CLKCTL_CCGR2]
 273         str r1, [r0, #CLKCTL_CCGR3]
 274         str r1, [r0, #CLKCTL_CCGR4]
 275         str r1, [r0, #CLKCTL_CCGR5]
 276         str r1, [r0, #CLKCTL_CCGR6]
 277 #if defined(CONFIG_MX53)
 278         str r1, [r0, #CLKCTL_CCGR7]
 279 #endif
 280
 281 #if defined(CONFIG_MX51)
 282         /* Use PLL 2 for UART's, get 66.5MHz from it */
 283         ldr r1, =0xA5A2A020
 284         str r1, [r0, #CLKCTL_CSCMR1]
 285         ldr r1, =0x00C30321
 286         str r1, [r0, #CLKCTL_CSCDR1]
 287 #elif defined(CONFIG_MX53)
 288         /* Switch peripheral to PLL2 */
 289         ldr r0, =CCM_BASE_ADDR
 290         ldr r1, =0x00808145
 291         orr r1, r1, #(2 << 10)
 292         orr r1, r1, #(0 << 16)
 293         orr r1, r1, #(1 << 19)
 294         str r1, [r0, #CLKCTL_CBCDR]
 295
 296         ldr r1, =0x00016154
 297         str r1, [r0, #CLKCTL_CBCMR]
 298         /* Change uart clk parent to pll2*/
 299         ldr r1, [r0, #CLKCTL_CSCMR1]
 300         and r1, r1, #0xfcffffff
 301         orr r1, r1, #0x01000000
 302         str r1, [r0, #CLKCTL_CSCMR1]
 303         ldr r1, [r0, #CLKCTL_CSCDR1]
 304         and r1, r1, #0xffffffc0
 305         orr r1, r1, #0x0a
 306         str r1, [r0, #CLKCTL_CSCDR1]
 307 #endif
 308         /* make sure divider effective */
 309 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
 310         cmp r1, #0x0
 311         bne 1b
 312
 313         mov r1, #0x0
 314         str r1, [r0, #CLKCTL_CCDR]
 315
 316         /* for cko - for ARM div by 8 */
 317         mov r1, #0x000A0000
 318         add r1, r1, #0x00000F0
 319         str r1, [r0, #CLKCTL_CCOSR]
 320 .endm
 321
 322 .macro setup_wdog
 323         ldr r0, =WDOG1_BASE_ADDR
 324         mov r1, #0x30
 325         strh r1, [r0]
 326 .endm
 327
 328 .section ".text.init", "x"
 329
 330 ENTRY(lowlevel_init)
 331 #if defined(CONFIG_MX51)
 332         ldr r0, =GPIO1_BASE_ADDR
 333         ldr r1, [r0, #0x0]
 334         orr r1, r1, #(1 << 23)
 335         str r1, [r0, #0x0]
 336         ldr r1, [r0, #0x4]
 337         orr r1, r1, #(1 << 23)
 338         str r1, [r0, #0x4]
 339 #endif
 340
 341         init_l2cc
 342
 343         init_aips
 344
 345         init_m4if
 346
 347         init_clock
 348
 349         /* r12 saved upper lr*/
 350         mov pc,lr
 351 ENDPROC(lowlevel_init)
 352
 353 /* Board level setting value */
 354 W_DP_OP_864:              .word DP_OP_864
 355 W_DP_MFD_864:             .word DP_MFD_864
 356 W_DP_MFN_864:             .word DP_MFN_864
 357 W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
 358 W_DP_OP_800:              .word DP_OP_800
 359 W_DP_MFD_800:             .word DP_MFD_800
 360 W_DP_MFN_800:             .word DP_MFN_800
 361 W_DP_OP_665:              .word DP_OP_665
 362 W_DP_MFD_665:             .word DP_MFD_665
 363 W_DP_MFN_665:             .word DP_MFN_665
 364 W_DP_OP_216:              .word DP_OP_216
 365 W_DP_MFD_216:             .word DP_MFD_216
 366 W_DP_MFN_216:             .word DP_MFN_216