2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS
, /* System PLL */
18 PLL_BUS
, /* System Bus PLL*/
19 PLL_USBOTG
, /* OTG USB PLL */
20 PLL_ENET
, /* ENET PLL */
21 PLL_AUDIO
, /* AUDIO PLL */
22 PLL_VIDEO
, /* AUDIO PLL */
25 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable
)
32 reg
= __raw_readl(&imx_ccm
->CCGR2
);
34 reg
|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
36 reg
&= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
37 __raw_writel(reg
, &imx_ccm
->CCGR2
);
41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg
)
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm
->CCGR4
,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
55 clrsetbits_le32(&imx_ccm
->cs2cdr
,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
,
61 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
63 clrbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
65 clrsetbits_le32(&imx_ccm
->cs2cdr
,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
71 setbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
73 setbits_le32(&imx_ccm
->CCGR4
,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
82 void enable_usboh3_clk(unsigned char enable
)
86 reg
= __raw_readl(&imx_ccm
->CCGR6
);
88 reg
|= MXC_CCM_CCGR6_USBOH3_MASK
;
90 reg
&= ~(MXC_CCM_CCGR6_USBOH3_MASK
);
91 __raw_writel(reg
, &imx_ccm
->CCGR6
);
95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
96 void enable_enet_clk(unsigned char enable
)
101 mask
= MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK
;
102 addr
= &imx_ccm
->CCGR0
;
103 } else if (is_mx6ul()) {
104 mask
= MXC_CCM_CCGR3_ENET_MASK
;
105 addr
= &imx_ccm
->CCGR3
;
107 mask
= MXC_CCM_CCGR1_ENET_MASK
;
108 addr
= &imx_ccm
->CCGR1
;
112 setbits_le32(addr
, mask
);
114 clrbits_le32(addr
, mask
);
118 #ifdef CONFIG_MXC_UART
119 void enable_uart_clk(unsigned char enable
)
123 if (is_mx6ul() || is_mx6ull())
124 mask
= MXC_CCM_CCGR5_UART_MASK
;
126 mask
= MXC_CCM_CCGR5_UART_MASK
| MXC_CCM_CCGR5_UART_SERIAL_MASK
;
129 setbits_le32(&imx_ccm
->CCGR5
, mask
);
131 clrbits_le32(&imx_ccm
->CCGR5
, mask
);
136 int enable_usdhc_clk(unsigned char enable
, unsigned bus_num
)
143 mask
= MXC_CCM_CCGR_CG_MASK
<< (bus_num
* 2 + 2);
145 setbits_le32(&imx_ccm
->CCGR6
, mask
);
147 clrbits_le32(&imx_ccm
->CCGR6
, mask
);
153 #ifdef CONFIG_SYS_I2C_MXC
154 /* i2c_num can be from 0 - 3 */
155 int enable_i2c_clk(unsigned char enable
, unsigned i2c_num
)
164 mask
= MXC_CCM_CCGR_CG_MASK
165 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
167 reg
= __raw_readl(&imx_ccm
->CCGR2
);
172 __raw_writel(reg
, &imx_ccm
->CCGR2
);
176 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
177 mask
= MXC_CCM_CCGR6_I2C4_MASK
;
178 addr
= &imx_ccm
->CCGR6
;
180 mask
= MXC_CCM_CCGR1_I2C4_SERIAL_MASK
;
181 addr
= &imx_ccm
->CCGR1
;
183 reg
= __raw_readl(addr
);
188 __raw_writel(reg
, addr
);
194 /* spi_num can be from 0 - SPI_MAX_NUM */
195 int enable_spi_clk(unsigned char enable
, unsigned spi_num
)
200 if (spi_num
> SPI_MAX_NUM
)
203 mask
= MXC_CCM_CCGR_CG_MASK
<< (spi_num
<< 1);
204 reg
= __raw_readl(&imx_ccm
->CCGR1
);
209 __raw_writel(reg
, &imx_ccm
->CCGR1
);
212 static u32
decode_pll(enum pll_clocks pll
, u32 infreq
)
214 u32 div
, test_div
, pll_num
, pll_denom
;
218 div
= __raw_readl(&imx_ccm
->analog_pll_sys
);
219 div
&= BM_ANADIG_PLL_SYS_DIV_SELECT
;
221 return (infreq
* div
) >> 1;
223 div
= __raw_readl(&imx_ccm
->analog_pll_528
);
224 div
&= BM_ANADIG_PLL_528_DIV_SELECT
;
226 return infreq
* (20 + (div
<< 1));
228 div
= __raw_readl(&imx_ccm
->analog_usb1_pll_480_ctrl
);
229 div
&= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT
;
231 return infreq
* (20 + (div
<< 1));
233 div
= __raw_readl(&imx_ccm
->analog_pll_enet
);
234 div
&= BM_ANADIG_PLL_ENET_DIV_SELECT
;
236 return 25000000 * (div
+ (div
>> 1) + 1);
238 div
= __raw_readl(&imx_ccm
->analog_pll_audio
);
239 if (!(div
& BM_ANADIG_PLL_AUDIO_ENABLE
))
241 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
242 if (div
& BM_ANADIG_PLL_AUDIO_BYPASS
)
244 pll_num
= __raw_readl(&imx_ccm
->analog_pll_audio_num
);
245 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_audio_denom
);
246 test_div
= (div
& BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
) >>
247 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
;
248 div
&= BM_ANADIG_PLL_AUDIO_DIV_SELECT
;
250 debug("Error test_div\n");
253 test_div
= 1 << (2 - test_div
);
255 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
257 div
= __raw_readl(&imx_ccm
->analog_pll_video
);
258 if (!(div
& BM_ANADIG_PLL_VIDEO_ENABLE
))
260 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
261 if (div
& BM_ANADIG_PLL_VIDEO_BYPASS
)
263 pll_num
= __raw_readl(&imx_ccm
->analog_pll_video_num
);
264 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_video_denom
);
265 test_div
= (div
& BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
) >>
266 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT
;
267 div
&= BM_ANADIG_PLL_VIDEO_DIV_SELECT
;
269 debug("Error test_div\n");
272 test_div
= 1 << (2 - test_div
);
274 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
280 static u32
mxc_get_pll_pfd(enum pll_clocks pll
, int pfd_num
)
287 if (!is_mx6ul() && !is_mx6ull()) {
289 /* No PFD3 on PLL2 */
293 div
= __raw_readl(&imx_ccm
->analog_pfd_528
);
294 freq
= (u64
)decode_pll(PLL_BUS
, MXC_HCLK
);
297 div
= __raw_readl(&imx_ccm
->analog_pfd_480
);
298 freq
= (u64
)decode_pll(PLL_USBOTG
, MXC_HCLK
);
301 /* No PFD on other PLL */
305 return lldiv(freq
* 18, (div
& ANATOP_PFD_FRAC_MASK(pfd_num
)) >>
306 ANATOP_PFD_FRAC_SHIFT(pfd_num
));
309 static u32
get_mcu_main_clk(void)
313 reg
= __raw_readl(&imx_ccm
->cacrr
);
314 reg
&= MXC_CCM_CACRR_ARM_PODF_MASK
;
315 reg
>>= MXC_CCM_CACRR_ARM_PODF_OFFSET
;
316 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
318 return freq
/ (reg
+ 1);
321 u32
get_periph_clk(void)
323 u32 reg
, div
= 0, freq
= 0;
325 reg
= __raw_readl(&imx_ccm
->cbcdr
);
326 if (reg
& MXC_CCM_CBCDR_PERIPH_CLK_SEL
) {
327 div
= (reg
& MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK
) >>
328 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET
;
329 reg
= __raw_readl(&imx_ccm
->cbcmr
);
330 reg
&= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK
;
331 reg
>>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET
;
335 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
345 reg
= __raw_readl(&imx_ccm
->cbcmr
);
346 reg
&= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
;
347 reg
>>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
;
351 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
354 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
357 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
360 /* static / 2 divider */
361 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
368 return freq
/ (div
+ 1);
371 static u32
get_ipg_clk(void)
375 reg
= __raw_readl(&imx_ccm
->cbcdr
);
376 reg
&= MXC_CCM_CBCDR_IPG_PODF_MASK
;
377 ipg_podf
= reg
>> MXC_CCM_CBCDR_IPG_PODF_OFFSET
;
379 return get_ahb_clk() / (ipg_podf
+ 1);
382 static u32
get_ipg_per_clk(void)
384 u32 reg
, perclk_podf
;
386 reg
= __raw_readl(&imx_ccm
->cscmr1
);
387 if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
388 is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
389 if (reg
& MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
)
390 return MXC_HCLK
; /* OSC 24Mhz */
393 perclk_podf
= reg
& MXC_CCM_CSCMR1_PERCLK_PODF_MASK
;
395 return get_ipg_clk() / (perclk_podf
+ 1);
398 static u32
get_uart_clk(void)
401 u32 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
) / 6; /* static divider */
402 reg
= __raw_readl(&imx_ccm
->cscdr1
);
404 if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
405 is_mx6sll() || is_mx6ull()) {
406 if (reg
& MXC_CCM_CSCDR1_UART_CLK_SEL
)
410 reg
&= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
;
411 uart_podf
= reg
>> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
;
413 return freq
/ (uart_podf
+ 1);
416 static u32
get_cspi_clk(void)
420 reg
= __raw_readl(&imx_ccm
->cscdr2
);
421 cspi_podf
= (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK
) >>
422 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET
;
424 if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
425 is_mx6sll() || is_mx6ull()) {
426 if (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK
)
427 return MXC_HCLK
/ (cspi_podf
+ 1);
430 return decode_pll(PLL_USBOTG
, MXC_HCLK
) / (8 * (cspi_podf
+ 1));
433 static u32
get_axi_clk(void)
435 u32 root_freq
, axi_podf
;
436 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
438 axi_podf
= cbcdr
& MXC_CCM_CBCDR_AXI_PODF_MASK
;
439 axi_podf
>>= MXC_CCM_CBCDR_AXI_PODF_OFFSET
;
441 if (cbcdr
& MXC_CCM_CBCDR_AXI_SEL
) {
442 if (cbcdr
& MXC_CCM_CBCDR_AXI_ALT_SEL
)
443 root_freq
= mxc_get_pll_pfd(PLL_USBOTG
, 1);
445 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
447 root_freq
= get_periph_clk();
449 return root_freq
/ (axi_podf
+ 1);
452 static u32
get_emi_slow_clk(void)
454 u32 emi_clk_sel
, emi_slow_podf
, cscmr1
, root_freq
= 0;
456 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
457 emi_clk_sel
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK
;
458 emi_clk_sel
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET
;
459 emi_slow_podf
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK
;
460 emi_slow_podf
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET
;
462 switch (emi_clk_sel
) {
464 root_freq
= get_axi_clk();
467 root_freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
470 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
473 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
477 return root_freq
/ (emi_slow_podf
+ 1);
480 static u32
get_mmdc_ch0_clk(void)
482 u32 cbcmr
= __raw_readl(&imx_ccm
->cbcmr
);
483 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
485 u32 freq
, podf
, per2_clk2_podf
, pmu_misc2_audio_div
;
487 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
489 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK
) >>
490 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET
;
491 if (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK_SEL
) {
492 per2_clk2_podf
= (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK
) >>
493 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET
;
495 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
498 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
500 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
501 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
503 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
508 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
) >>
509 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
) {
511 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
514 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
517 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
521 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) >> 1;
525 pmu_misc2_audio_div
= PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm
->pmu_misc2
));
526 switch (pmu_misc2_audio_div
) {
529 pmu_misc2_audio_div
= 1;
532 pmu_misc2_audio_div
= 2;
535 pmu_misc2_audio_div
= 4;
538 freq
= decode_pll(PLL_AUDIO
, MXC_HCLK
) /
543 return freq
/ (podf
+ 1) / (per2_clk2_podf
+ 1);
545 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK
) >>
546 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET
;
547 return get_periph_clk() / (podf
+ 1);
551 #if defined(CONFIG_VIDEO_MXS)
552 static int enable_pll_video(u32 pll_div
, u32 pll_num
, u32 pll_denom
,
558 debug("pll5 div = %d, num = %d, denom = %d\n",
559 pll_div
, pll_num
, pll_denom
);
561 /* Power up PLL5 video */
562 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN
|
563 BM_ANADIG_PLL_VIDEO_BYPASS
|
564 BM_ANADIG_PLL_VIDEO_DIV_SELECT
|
565 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
,
566 &imx_ccm
->analog_pll_video_clr
);
568 /* Set div, num and denom */
571 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
572 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
573 &imx_ccm
->analog_pll_video_set
);
576 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
577 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
578 &imx_ccm
->analog_pll_video_set
);
581 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
582 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
583 &imx_ccm
->analog_pll_video_set
);
586 puts("Wrong test_div!\n");
590 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num
),
591 &imx_ccm
->analog_pll_video_num
);
592 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom
),
593 &imx_ccm
->analog_pll_video_denom
);
596 start
= get_timer(0); /* Get current timestamp */
599 reg
= readl(&imx_ccm
->analog_pll_video
);
600 if (reg
& BM_ANADIG_PLL_VIDEO_LOCK
) {
602 writel(BM_ANADIG_PLL_VIDEO_ENABLE
,
603 &imx_ccm
->analog_pll_video_set
);
606 } while (get_timer(0) < (start
+ 10)); /* Wait 10ms */
608 puts("Lock PLL5 timeout\n");
614 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
616 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
618 void mxs_set_lcdclk(u32 base_addr
, u32 freq
)
621 u32 hck
= MXC_HCLK
/ 1000;
622 /* DIV_SELECT ranges from 27 to 54 */
626 u32 i
, j
, max_pred
= 8, max_postd
= 8, pred
= 1, postd
= 1;
627 u32 pll_div
, pll_num
, pll_denom
, post_div
= 1;
629 debug("mxs_set_lcdclk, freq = %dKHz\n", freq
);
631 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
633 debug("This chip not support lcd!\n");
638 if (base_addr
== LCDIF1_BASE_ADDR
) {
639 reg
= readl(&imx_ccm
->cscdr2
);
640 /* Can't change clocks when clock not from pre-mux */
641 if ((reg
& MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
) != 0)
647 reg
= readl(&imx_ccm
->cscdr2
);
648 /* Can't change clocks when clock not from pre-mux */
649 if ((reg
& MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
) != 0)
653 temp
= freq
* max_pred
* max_postd
;
656 * Register: PLL_VIDEO
657 * Bit Field: POST_DIV_SELECT
658 * 00 — Divide by 4.
659 * 01 — Divide by 2.
660 * 10 — Divide by 1.
662 * No need to check post_div(1)
664 for (post_div
= 2; post_div
<= 4; post_div
<<= 1) {
665 if ((temp
* post_div
) > min
) {
672 printf("Fail to set rate to %dkhz", freq
);
677 /* Choose the best pred and postd to match freq for lcd */
678 for (i
= 1; i
<= max_pred
; i
++) {
679 for (j
= 1; j
<= max_postd
; j
++) {
681 if (temp
> max
|| temp
< min
)
683 if (best
== 0 || temp
< best
) {
692 printf("Fail to set rate to %dKHz", freq
);
696 debug("best %d, pred = %d, postd = %d\n", best
, pred
, postd
);
698 pll_div
= best
/ hck
;
700 pll_num
= (best
- hck
* pll_div
) * pll_denom
/ hck
;
704 * (24MHz * (pll_div + --------- ))
706 *freq KHz = --------------------------------
707 * post_div * pred * postd * 1000
710 if (base_addr
== LCDIF1_BASE_ADDR
) {
711 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
714 enable_lcdif_clock(base_addr
, 0);
716 /* Select pre-lcd clock to PLL5 and set pre divider */
717 clrsetbits_le32(&imx_ccm
->cscdr2
,
718 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK
|
719 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK
,
720 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET
) |
722 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET
));
724 /* Set the post divider */
725 clrsetbits_le32(&imx_ccm
->cbcmr
,
726 MXC_CCM_CBCMR_LCDIF1_PODF_MASK
,
728 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET
));
730 /* Select pre-lcd clock to PLL5 and set pre divider */
731 clrsetbits_le32(&imx_ccm
->cscdr2
,
732 MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK
|
733 MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK
,
734 (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET
) |
736 MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET
));
738 /* Set the post divider */
739 clrsetbits_le32(&imx_ccm
->cscmr1
,
740 MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK
,
741 (((postd
- 1)^0x6) <<
742 MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET
));
745 enable_lcdif_clock(base_addr
, 1);
746 } else if (is_mx6sx()) {
747 /* Setting LCDIF2 for i.MX6SX */
748 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
751 enable_lcdif_clock(base_addr
, 0);
752 /* Select pre-lcd clock to PLL5 and set pre divider */
753 clrsetbits_le32(&imx_ccm
->cscdr2
,
754 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK
|
755 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK
,
756 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET
) |
758 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET
));
760 /* Set the post divider */
761 clrsetbits_le32(&imx_ccm
->cscmr1
,
762 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK
,
764 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET
));
766 enable_lcdif_clock(base_addr
, 1);
770 int enable_lcdif_clock(u32 base_addr
, bool enable
)
773 u32 lcdif_clk_sel_mask
, lcdif_ccgr3_mask
;
776 if ((base_addr
!= LCDIF1_BASE_ADDR
) &&
777 (base_addr
!= LCDIF2_BASE_ADDR
)) {
778 puts("Wrong LCD interface!\n");
781 /* Set to pre-mux clock at default */
782 lcdif_clk_sel_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
783 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
:
784 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
785 lcdif_ccgr3_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
786 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK
|
787 MXC_CCM_CCGR3_DISP_AXI_MASK
) :
788 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK
|
789 MXC_CCM_CCGR3_DISP_AXI_MASK
);
790 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
791 if (base_addr
!= LCDIF1_BASE_ADDR
) {
792 puts("Wrong LCD interface!\n");
795 /* Set to pre-mux clock at default */
796 lcdif_clk_sel_mask
= MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
797 lcdif_ccgr3_mask
= MXC_CCM_CCGR3_LCDIF1_PIX_MASK
;
798 } else if (is_mx6sl()) {
799 if (base_addr
!= LCDIF1_BASE_ADDR
) {
800 puts("Wrong LCD interface!\n");
804 reg
= readl(&imx_ccm
->CCGR3
);
805 reg
&= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK
|
806 MXC_CCM_CCGR3_LCDIF_PIX_MASK
);
807 writel(reg
, &imx_ccm
->CCGR3
);
810 reg
= readl(&imx_ccm
->cscdr3
);
811 reg
&= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK
;
812 reg
|= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET
;
813 writel(reg
, &imx_ccm
->cscdr3
);
815 reg
= readl(&imx_ccm
->CCGR3
);
816 reg
|= MXC_CCM_CCGR3_LCDIF_AXI_MASK
|
817 MXC_CCM_CCGR3_LCDIF_PIX_MASK
;
818 writel(reg
, &imx_ccm
->CCGR3
);
826 /* Gate LCDIF clock first */
827 reg
= readl(&imx_ccm
->CCGR3
);
828 reg
&= ~lcdif_ccgr3_mask
;
829 writel(reg
, &imx_ccm
->CCGR3
);
831 reg
= readl(&imx_ccm
->CCGR2
);
832 reg
&= ~MXC_CCM_CCGR2_LCD_MASK
;
833 writel(reg
, &imx_ccm
->CCGR2
);
837 reg
= readl(&imx_ccm
->cscdr2
);
838 reg
&= ~lcdif_clk_sel_mask
;
839 writel(reg
, &imx_ccm
->cscdr2
);
841 /* Enable the LCDIF pix clock */
842 reg
= readl(&imx_ccm
->CCGR3
);
843 reg
|= lcdif_ccgr3_mask
;
844 writel(reg
, &imx_ccm
->CCGR3
);
846 reg
= readl(&imx_ccm
->CCGR2
);
847 reg
|= MXC_CCM_CCGR2_LCD_MASK
;
848 writel(reg
, &imx_ccm
->CCGR2
);
855 #ifdef CONFIG_FSL_QSPI
856 /* qspi_num can be from 0 - 1 */
857 void enable_qspi_clk(int qspi_num
)
860 /* Enable QuadSPI clock */
863 /* disable the clock gate */
864 clrbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
866 /* set 50M : (50 = 396 / 2 / 4) */
867 reg
= readl(&imx_ccm
->cscmr1
);
868 reg
&= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK
|
869 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK
);
870 reg
|= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET
) |
871 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET
));
872 writel(reg
, &imx_ccm
->cscmr1
);
874 /* enable the clock gate */
875 setbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
879 * disable the clock gate
880 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
881 * disable both of them.
883 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
884 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
886 /* set 50M : (50 = 396 / 2 / 4) */
887 reg
= readl(&imx_ccm
->cs2cdr
);
888 reg
&= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
889 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
890 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
);
891 reg
|= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
892 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
893 writel(reg
, &imx_ccm
->cs2cdr
);
895 /*enable the clock gate*/
896 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
897 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
905 #ifdef CONFIG_FEC_MXC
906 int enable_fec_anatop_clock(int fec_id
, enum enet_freq freq
)
909 s32 timeout
= 100000;
911 struct anatop_regs __iomem
*anatop
=
912 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
914 if (freq
< ENET_25MHZ
|| freq
> ENET_125MHZ
)
917 reg
= readl(&anatop
->pll_enet
);
920 reg
&= ~BM_ANADIG_PLL_ENET_DIV_SELECT
;
921 reg
|= BF_ANADIG_PLL_ENET_DIV_SELECT(freq
);
922 } else if (fec_id
== 1) {
923 /* Only i.MX6SX/UL support ENET2 */
924 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
926 reg
&= ~BM_ANADIG_PLL_ENET2_DIV_SELECT
;
927 reg
|= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq
);
932 if ((reg
& BM_ANADIG_PLL_ENET_POWERDOWN
) ||
933 (!(reg
& BM_ANADIG_PLL_ENET_LOCK
))) {
934 reg
&= ~BM_ANADIG_PLL_ENET_POWERDOWN
;
935 writel(reg
, &anatop
->pll_enet
);
937 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_ENET_LOCK
)
944 /* Enable FEC clock */
946 reg
|= BM_ANADIG_PLL_ENET_ENABLE
;
948 reg
|= BM_ANADIG_PLL_ENET2_ENABLE
;
949 reg
&= ~BM_ANADIG_PLL_ENET_BYPASS
;
950 writel(reg
, &anatop
->pll_enet
);
953 /* Disable enet system clcok before switching clock parent */
954 reg
= readl(&imx_ccm
->CCGR3
);
955 reg
&= ~MXC_CCM_CCGR3_ENET_MASK
;
956 writel(reg
, &imx_ccm
->CCGR3
);
959 * Set enet ahb clock to 200MHz
960 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
962 reg
= readl(&imx_ccm
->chsccdr
);
963 reg
&= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
964 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
965 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK
);
967 reg
|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET
);
969 reg
|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET
);
970 reg
|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET
);
971 writel(reg
, &imx_ccm
->chsccdr
);
973 /* Enable enet system clock */
974 reg
= readl(&imx_ccm
->CCGR3
);
975 reg
|= MXC_CCM_CCGR3_ENET_MASK
;
976 writel(reg
, &imx_ccm
->CCGR3
);
982 static u32
get_usdhc_clk(u32 port
)
984 u32 root_freq
= 0, usdhc_podf
= 0, clk_sel
= 0;
985 u32 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
986 u32 cscdr1
= __raw_readl(&imx_ccm
->cscdr1
);
988 if (is_mx6ul() || is_mx6ull()) {
1000 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC1_PODF_MASK
) >>
1001 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET
;
1002 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC1_CLK_SEL
;
1006 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC2_PODF_MASK
) >>
1007 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET
;
1008 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC2_CLK_SEL
;
1012 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC3_PODF_MASK
) >>
1013 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET
;
1014 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC3_CLK_SEL
;
1018 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC4_PODF_MASK
) >>
1019 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET
;
1020 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC4_CLK_SEL
;
1028 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
1030 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
1032 return root_freq
/ (usdhc_podf
+ 1);
1035 u32
imx_get_uartclk(void)
1037 return get_uart_clk();
1040 u32
imx_get_fecclk(void)
1042 return mxc_get_clock(MXC_IPG_CLK
);
1045 #if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
1046 static int enable_enet_pll(uint32_t en
)
1048 struct mxc_ccm_reg
*const imx_ccm
1049 = (struct mxc_ccm_reg
*) CCM_BASE_ADDR
;
1050 s32 timeout
= 100000;
1054 reg
= readl(&imx_ccm
->analog_pll_enet
);
1055 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
1056 writel(reg
, &imx_ccm
->analog_pll_enet
);
1057 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
1059 if (readl(&imx_ccm
->analog_pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
1064 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
1065 writel(reg
, &imx_ccm
->analog_pll_enet
);
1067 writel(reg
, &imx_ccm
->analog_pll_enet
);
1073 static void ungate_sata_clock(void)
1075 struct mxc_ccm_reg
*const imx_ccm
=
1076 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1078 /* Enable SATA clock. */
1079 setbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1082 int enable_sata_clock(void)
1084 ungate_sata_clock();
1085 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
);
1088 void disable_sata_clock(void)
1090 struct mxc_ccm_reg
*const imx_ccm
=
1091 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1093 clrbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1097 #ifdef CONFIG_PCIE_IMX
1098 static void ungate_pcie_clock(void)
1100 struct mxc_ccm_reg
*const imx_ccm
=
1101 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1103 /* Enable PCIe clock. */
1104 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_PCIE_MASK
);
1107 int enable_pcie_clock(void)
1109 struct anatop_regs
*anatop_regs
=
1110 (struct anatop_regs
*)ANATOP_BASE_ADDR
;
1111 struct mxc_ccm_reg
*ccm_regs
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1117 * The register ANATOP_MISC1 is not documented in the Freescale
1118 * MX6RM. The register that is mapped in the ANATOP space and
1119 * marked as ANATOP_MISC1 is actually documented in the PMU section
1120 * of the datasheet as PMU_MISC1.
1122 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1123 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1124 * for PCI express link that is clocked from the i.MX6.
1126 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1127 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1128 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1129 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1130 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1133 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF
;
1135 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF
;
1137 clrsetbits_le32(&anatop_regs
->ana_misc1
,
1138 ANADIG_ANA_MISC1_LVDSCLK1_IBEN
|
1139 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK
,
1140 ANADIG_ANA_MISC1_LVDSCLK1_OBEN
| lvds1_clk_sel
);
1142 /* PCIe reference clock sourced from AXI. */
1143 clrbits_le32(&ccm_regs
->cbcmr
, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL
);
1145 /* Party time! Ungate the clock to the PCIe. */
1147 ungate_sata_clock();
1149 ungate_pcie_clock();
1151 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
|
1152 BM_ANADIG_PLL_ENET_ENABLE_PCIE
);
1156 #ifdef CONFIG_SECURE_BOOT
1157 void hab_caam_clock_enable(unsigned char enable
)
1161 if (is_mx6ull() || is_mx6sll()) {
1162 /* CG5, DCP clock */
1163 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1165 reg
|= MXC_CCM_CCGR0_DCP_CLK_MASK
;
1167 reg
&= ~MXC_CCM_CCGR0_DCP_CLK_MASK
;
1168 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1170 /* CG4 ~ CG6, CAAM clocks */
1171 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1173 reg
|= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1174 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1175 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1177 reg
&= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1178 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1179 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1180 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1184 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1186 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1188 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1189 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1193 static void enable_pll3(void)
1195 struct anatop_regs __iomem
*anatop
=
1196 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
1198 /* make sure pll3 is enabled */
1199 if ((readl(&anatop
->usb1_pll_480_ctrl
) &
1200 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0) {
1201 /* enable pll's power */
1202 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER
,
1203 &anatop
->usb1_pll_480_ctrl_set
);
1204 writel(0x80, &anatop
->ana_misc2_clr
);
1205 /* wait for pll lock */
1206 while ((readl(&anatop
->usb1_pll_480_ctrl
) &
1207 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0)
1209 /* disable bypass */
1210 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS
,
1211 &anatop
->usb1_pll_480_ctrl_clr
);
1212 /* enable pll output */
1213 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE
,
1214 &anatop
->usb1_pll_480_ctrl_set
);
1218 void enable_thermal_clk(void)
1223 unsigned int mxc_get_clock(enum mxc_clock clk
)
1227 return get_mcu_main_clk();
1229 return get_periph_clk();
1231 return get_ahb_clk();
1233 return get_ipg_clk();
1234 case MXC_IPG_PERCLK
:
1236 return get_ipg_per_clk();
1238 return get_uart_clk();
1240 return get_cspi_clk();
1242 return get_axi_clk();
1243 case MXC_EMI_SLOW_CLK
:
1244 return get_emi_slow_clk();
1246 return get_mmdc_ch0_clk();
1248 return get_usdhc_clk(0);
1249 case MXC_ESDHC2_CLK
:
1250 return get_usdhc_clk(1);
1251 case MXC_ESDHC3_CLK
:
1252 return get_usdhc_clk(2);
1253 case MXC_ESDHC4_CLK
:
1254 return get_usdhc_clk(3);
1256 return get_ahb_clk();
1258 printf("Unsupported MXC CLK: %d\n", clk
);
1266 * Dump some core clockes.
1268 int do_mx6_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
1271 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
1272 printf("PLL_SYS %8d MHz\n", freq
/ 1000000);
1273 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
1274 printf("PLL_BUS %8d MHz\n", freq
/ 1000000);
1275 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
1276 printf("PLL_OTG %8d MHz\n", freq
/ 1000000);
1277 freq
= decode_pll(PLL_ENET
, MXC_HCLK
);
1278 printf("PLL_NET %8d MHz\n", freq
/ 1000000);
1281 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK
) / 1000);
1282 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK
) / 1000);
1283 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK
) / 1000);
1284 #ifdef CONFIG_MXC_SPI
1285 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK
) / 1000);
1287 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000);
1288 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK
) / 1000);
1289 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK
) / 1000);
1290 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK
) / 1000);
1291 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK
) / 1000);
1292 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK
) / 1000);
1293 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK
) / 1000);
1294 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK
) / 1000);
1295 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK
) / 1000);
1300 #ifndef CONFIG_MX6SX
1301 void enable_ipu_clock(void)
1303 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1305 reg
= readl(&mxc_ccm
->CCGR3
);
1306 reg
|= MXC_CCM_CCGR3_IPU1_IPU_MASK
;
1307 writel(reg
, &mxc_ccm
->CCGR3
);
1310 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_PRG_CLK0_MASK
);
1311 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_IPU2_IPU_MASK
);
1316 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1317 defined(CONFIG_MX6S)
1318 static void disable_ldb_di_clock_sources(void)
1320 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1323 /* Make sure PFDs are disabled at boot. */
1324 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1325 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1330 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1332 /* Disable PLL3 PFDs */
1333 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1335 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1338 reg
= readl(&mxc_ccm
->analog_pll_video
);
1340 writel(reg
, &mxc_ccm
->analog_pll_video
);
1343 static void enable_ldb_di_clock_sources(void)
1345 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1348 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1350 reg
&= ~(0x80008080);
1352 reg
&= ~(0x80808080);
1353 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1355 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1356 reg
&= ~(0x80808080);
1357 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1361 * Try call this function as early in the boot process as possible since the
1362 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1364 void select_ldb_di_clock_source(enum ldb_di_clock clk
)
1366 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1370 * Need to follow a strict procedure when changing the LDB
1371 * clock, else we can introduce a glitch. Things to keep in
1373 * 1. The current and new parent clocks must be disabled.
1374 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1376 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1377 * the top four options are in one mux and the PLL3 option along
1378 * with another option is in the second mux. There is third mux
1379 * used to decide between the first and second mux.
1380 * The code below switches the parent to the bottom mux first
1381 * and then manipulates the top mux. This ensures that no glitch
1382 * will enter the divider.
1384 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1385 * for this clock. The only way to disable this clock is to move
1386 * it to pll3_sw_clk and then to disable pll3_sw_clk
1387 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1390 /* Disable all ldb_di clock parents */
1391 disable_ldb_di_clock_sources();
1393 /* Set MMDC_CH1 mask bit */
1394 reg
= readl(&mxc_ccm
->ccdr
);
1395 reg
|= MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1396 writel(reg
, &mxc_ccm
->ccdr
);
1398 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1399 reg
= readl(&mxc_ccm
->cbcmr
);
1400 reg
&= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
;
1401 writel(reg
, &mxc_ccm
->cbcmr
);
1404 * Set the periph2_clk_sel to the top mux so that
1405 * mmdc_ch1 is from pll3_sw_clk.
1407 reg
= readl(&mxc_ccm
->cbcdr
);
1408 reg
|= MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1409 writel(reg
, &mxc_ccm
->cbcdr
);
1411 /* Wait for the clock switch */
1412 while (readl(&mxc_ccm
->cdhipr
))
1414 /* Disable pll3_sw_clk by selecting bypass clock source */
1415 reg
= readl(&mxc_ccm
->ccsr
);
1416 reg
|= MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1417 writel(reg
, &mxc_ccm
->ccsr
);
1419 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1420 reg
= readl(&mxc_ccm
->cs2cdr
);
1421 reg
|= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1422 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1423 writel(reg
, &mxc_ccm
->cs2cdr
);
1425 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1426 reg
= readl(&mxc_ccm
->cs2cdr
);
1427 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1428 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1429 reg
|= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1430 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1431 writel(reg
, &mxc_ccm
->cs2cdr
);
1433 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1434 reg
= readl(&mxc_ccm
->cs2cdr
);
1435 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1436 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1437 reg
|= ((clk
<< MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1438 | (clk
<< MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1439 writel(reg
, &mxc_ccm
->cs2cdr
);
1441 /* Unbypass pll3_sw_clk */
1442 reg
= readl(&mxc_ccm
->ccsr
);
1443 reg
&= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1444 writel(reg
, &mxc_ccm
->ccsr
);
1447 * Set the periph2_clk_sel back to the bottom mux so that
1448 * mmdc_ch1 is from its original parent.
1450 reg
= readl(&mxc_ccm
->cbcdr
);
1451 reg
&= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1452 writel(reg
, &mxc_ccm
->cbcdr
);
1454 /* Wait for the clock switch */
1455 while (readl(&mxc_ccm
->cdhipr
))
1457 /* Clear MMDC_CH1 mask bit */
1458 reg
= readl(&mxc_ccm
->ccdr
);
1459 reg
&= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1460 writel(reg
, &mxc_ccm
->ccdr
);
1462 enable_ldb_di_clock_sources();
1466 #ifdef CONFIG_MTD_NOR_FLASH
1467 void enable_eim_clk(unsigned char enable
)
1471 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1473 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1475 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1476 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1480 /***************************************************/
1483 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx6_showclocks
,