2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS
, /* System PLL */
18 PLL_BUS
, /* System Bus PLL*/
19 PLL_USBOTG
, /* OTG USB PLL */
20 PLL_ENET
, /* ENET PLL */
23 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable
)
30 reg
= __raw_readl(&imx_ccm
->CCGR2
);
32 reg
|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
34 reg
&= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
35 __raw_writel(reg
, &imx_ccm
->CCGR2
);
39 void enable_usboh3_clk(unsigned char enable
)
43 reg
= __raw_readl(&imx_ccm
->CCGR6
);
45 reg
|= MXC_CCM_CCGR6_USBOH3_MASK
;
47 reg
&= ~(MXC_CCM_CCGR6_USBOH3_MASK
);
48 __raw_writel(reg
, &imx_ccm
->CCGR6
);
52 #ifdef CONFIG_SYS_I2C_MXC
53 /* i2c_num can be from 0 - 2 */
54 int enable_i2c_clk(unsigned char enable
, unsigned i2c_num
)
62 mask
= MXC_CCM_CCGR_CG_MASK
63 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+ (i2c_num
<< 1));
64 reg
= __raw_readl(&imx_ccm
->CCGR2
);
69 __raw_writel(reg
, &imx_ccm
->CCGR2
);
74 /* spi_num can be from 0 - SPI_MAX_NUM */
75 int enable_spi_clk(unsigned char enable
, unsigned spi_num
)
80 if (spi_num
> SPI_MAX_NUM
)
83 mask
= MXC_CCM_CCGR_CG_MASK
<< (spi_num
<< 1);
84 reg
= __raw_readl(&imx_ccm
->CCGR1
);
89 __raw_writel(reg
, &imx_ccm
->CCGR1
);
92 static u32
decode_pll(enum pll_clocks pll
, u32 infreq
)
98 div
= __raw_readl(&imx_ccm
->analog_pll_sys
);
99 div
&= BM_ANADIG_PLL_SYS_DIV_SELECT
;
101 return (infreq
* div
) >> 1;
103 div
= __raw_readl(&imx_ccm
->analog_pll_528
);
104 div
&= BM_ANADIG_PLL_528_DIV_SELECT
;
106 return infreq
* (20 + (div
<< 1));
108 div
= __raw_readl(&imx_ccm
->analog_usb1_pll_480_ctrl
);
109 div
&= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT
;
111 return infreq
* (20 + (div
<< 1));
113 div
= __raw_readl(&imx_ccm
->analog_pll_enet
);
114 div
&= BM_ANADIG_PLL_ENET_DIV_SELECT
;
116 return 25000000 * (div
+ (div
>> 1) + 1);
122 static u32
mxc_get_pll_pfd(enum pll_clocks pll
, int pfd_num
)
130 /* No PFD3 on PPL2 */
133 div
= __raw_readl(&imx_ccm
->analog_pfd_528
);
134 freq
= (u64
)decode_pll(PLL_BUS
, MXC_HCLK
);
137 div
= __raw_readl(&imx_ccm
->analog_pfd_480
);
138 freq
= (u64
)decode_pll(PLL_USBOTG
, MXC_HCLK
);
141 /* No PFD on other PLL */
145 return lldiv(freq
* 18, (div
& ANATOP_PFD_FRAC_MASK(pfd_num
)) >>
146 ANATOP_PFD_FRAC_SHIFT(pfd_num
));
149 static u32
get_mcu_main_clk(void)
153 reg
= __raw_readl(&imx_ccm
->cacrr
);
154 reg
&= MXC_CCM_CACRR_ARM_PODF_MASK
;
155 reg
>>= MXC_CCM_CACRR_ARM_PODF_OFFSET
;
156 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
158 return freq
/ (reg
+ 1);
161 u32
get_periph_clk(void)
165 reg
= __raw_readl(&imx_ccm
->cbcdr
);
166 if (reg
& MXC_CCM_CBCDR_PERIPH_CLK_SEL
) {
167 reg
= __raw_readl(&imx_ccm
->cbcmr
);
168 reg
&= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK
;
169 reg
>>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET
;
173 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
183 reg
= __raw_readl(&imx_ccm
->cbcmr
);
184 reg
&= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
;
185 reg
>>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
;
189 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
192 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
195 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
198 /* static / 2 divider */
199 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
209 static u32
get_ipg_clk(void)
213 reg
= __raw_readl(&imx_ccm
->cbcdr
);
214 reg
&= MXC_CCM_CBCDR_IPG_PODF_MASK
;
215 ipg_podf
= reg
>> MXC_CCM_CBCDR_IPG_PODF_OFFSET
;
217 return get_ahb_clk() / (ipg_podf
+ 1);
220 static u32
get_ipg_per_clk(void)
222 u32 reg
, perclk_podf
;
224 reg
= __raw_readl(&imx_ccm
->cscmr1
);
225 perclk_podf
= reg
& MXC_CCM_CSCMR1_PERCLK_PODF_MASK
;
227 return get_ipg_clk() / (perclk_podf
+ 1);
230 static u32
get_uart_clk(void)
233 u32 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
) / 6; /* static divider */
234 reg
= __raw_readl(&imx_ccm
->cscdr1
);
235 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
236 if (reg
& MXC_CCM_CSCDR1_UART_CLK_SEL
)
239 reg
&= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
;
240 uart_podf
= reg
>> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
;
242 return freq
/ (uart_podf
+ 1);
245 static u32
get_cspi_clk(void)
249 reg
= __raw_readl(&imx_ccm
->cscdr2
);
250 reg
&= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK
;
251 cspi_podf
= reg
>> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET
;
253 return decode_pll(PLL_USBOTG
, MXC_HCLK
) / (8 * (cspi_podf
+ 1));
256 static u32
get_axi_clk(void)
258 u32 root_freq
, axi_podf
;
259 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
261 axi_podf
= cbcdr
& MXC_CCM_CBCDR_AXI_PODF_MASK
;
262 axi_podf
>>= MXC_CCM_CBCDR_AXI_PODF_OFFSET
;
264 if (cbcdr
& MXC_CCM_CBCDR_AXI_SEL
) {
265 if (cbcdr
& MXC_CCM_CBCDR_AXI_ALT_SEL
)
266 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
268 root_freq
= mxc_get_pll_pfd(PLL_USBOTG
, 1);
270 root_freq
= get_periph_clk();
272 return root_freq
/ (axi_podf
+ 1);
275 static u32
get_emi_slow_clk(void)
277 u32 emi_clk_sel
, emi_slow_podf
, cscmr1
, root_freq
= 0;
279 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
280 emi_clk_sel
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK
;
281 emi_clk_sel
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET
;
282 emi_slow_podf
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK
;
283 emi_slow_podf
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET
;
285 switch (emi_clk_sel
) {
287 root_freq
= get_axi_clk();
290 root_freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
293 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
296 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
300 return root_freq
/ (emi_slow_podf
+ 1);
303 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
304 static u32
get_mmdc_ch0_clk(void)
306 u32 cbcmr
= __raw_readl(&imx_ccm
->cbcmr
);
307 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
310 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK
) \
311 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET
;
313 switch ((cbcmr
& MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
) >>
314 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
) {
316 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
319 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
322 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
325 /* static / 2 divider */
326 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
329 return freq
/ (podf
+ 1);
333 static u32
get_mmdc_ch0_clk(void)
335 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
336 u32 mmdc_ch0_podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK
) >>
337 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET
;
339 return get_periph_clk() / (mmdc_ch0_podf
+ 1);
343 #ifdef CONFIG_FEC_MXC
344 int enable_fec_anatop_clock(enum enet_freq freq
)
347 s32 timeout
= 100000;
349 struct anatop_regs __iomem
*anatop
=
350 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
352 if (freq
< ENET_25MHz
|| freq
> ENET_125MHz
)
355 reg
= readl(&anatop
->pll_enet
);
356 reg
&= ~BM_ANADIG_PLL_ENET_DIV_SELECT
;
359 if ((reg
& BM_ANADIG_PLL_ENET_POWERDOWN
) ||
360 (!(reg
& BM_ANADIG_PLL_ENET_LOCK
))) {
361 reg
&= ~BM_ANADIG_PLL_ENET_POWERDOWN
;
362 writel(reg
, &anatop
->pll_enet
);
364 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_ENET_LOCK
)
371 /* Enable FEC clock */
372 reg
|= BM_ANADIG_PLL_ENET_ENABLE
;
373 reg
&= ~BM_ANADIG_PLL_ENET_BYPASS
;
374 writel(reg
, &anatop
->pll_enet
);
378 * Set enet ahb clock to 200MHz
379 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
381 reg
= readl(&imx_ccm
->chsccdr
);
382 reg
&= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
383 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
384 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK
);
386 reg
|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET
);
388 reg
|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET
);
389 reg
|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET
);
390 writel(reg
, &imx_ccm
->chsccdr
);
392 /* Enable enet system clock */
393 reg
= readl(&imx_ccm
->CCGR3
);
394 reg
|= MXC_CCM_CCGR3_ENET_MASK
;
395 writel(reg
, &imx_ccm
->CCGR3
);
401 static u32
get_usdhc_clk(u32 port
)
403 u32 root_freq
= 0, usdhc_podf
= 0, clk_sel
= 0;
404 u32 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
405 u32 cscdr1
= __raw_readl(&imx_ccm
->cscdr1
);
409 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC1_PODF_MASK
) >>
410 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET
;
411 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC1_CLK_SEL
;
415 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC2_PODF_MASK
) >>
416 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET
;
417 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC2_CLK_SEL
;
421 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC3_PODF_MASK
) >>
422 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET
;
423 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC3_CLK_SEL
;
427 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC4_PODF_MASK
) >>
428 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET
;
429 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC4_CLK_SEL
;
437 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
439 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
441 return root_freq
/ (usdhc_podf
+ 1);
444 u32
imx_get_uartclk(void)
446 return get_uart_clk();
449 u32
imx_get_fecclk(void)
451 return mxc_get_clock(MXC_IPG_CLK
);
454 static int enable_enet_pll(uint32_t en
)
456 struct mxc_ccm_reg
*const imx_ccm
457 = (struct mxc_ccm_reg
*) CCM_BASE_ADDR
;
458 s32 timeout
= 100000;
462 reg
= readl(&imx_ccm
->analog_pll_enet
);
463 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
464 writel(reg
, &imx_ccm
->analog_pll_enet
);
465 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
467 if (readl(&imx_ccm
->analog_pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
472 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
473 writel(reg
, &imx_ccm
->analog_pll_enet
);
475 writel(reg
, &imx_ccm
->analog_pll_enet
);
480 static void ungate_sata_clock(void)
482 struct mxc_ccm_reg
*const imx_ccm
=
483 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
485 /* Enable SATA clock. */
486 setbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
490 static void ungate_pcie_clock(void)
492 struct mxc_ccm_reg
*const imx_ccm
=
493 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
495 /* Enable PCIe clock. */
496 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_PCIE_MASK
);
500 int enable_sata_clock(void)
503 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
);
507 int enable_pcie_clock(void)
509 struct anatop_regs
*anatop_regs
=
510 (struct anatop_regs
*)ANATOP_BASE_ADDR
;
511 struct mxc_ccm_reg
*ccm_regs
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
516 * The register ANATOP_MISC1 is not documented in the Freescale
517 * MX6RM. The register that is mapped in the ANATOP space and
518 * marked as ANATOP_MISC1 is actually documented in the PMU section
519 * of the datasheet as PMU_MISC1.
521 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
522 * enable clock OUTPUT. This is important for PCI express link that
523 * is clocked from the i.MX6.
525 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
526 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
527 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
528 clrsetbits_le32(&anatop_regs
->ana_misc1
,
529 ANADIG_ANA_MISC1_LVDSCLK1_IBEN
|
530 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK
,
531 ANADIG_ANA_MISC1_LVDSCLK1_OBEN
| 0xb);
533 /* PCIe reference clock sourced from AXI. */
534 clrbits_le32(&ccm_regs
->cbcmr
, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL
);
536 /* Party time! Ungate the clock to the PCIe. */
542 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
|
543 BM_ANADIG_PLL_ENET_ENABLE_PCIE
);
546 unsigned int mxc_get_clock(enum mxc_clock clk
)
550 return get_mcu_main_clk();
552 return get_periph_clk();
554 return get_ahb_clk();
556 return get_ipg_clk();
559 return get_ipg_per_clk();
561 return get_uart_clk();
563 return get_cspi_clk();
565 return get_axi_clk();
566 case MXC_EMI_SLOW_CLK
:
567 return get_emi_slow_clk();
569 return get_mmdc_ch0_clk();
571 return get_usdhc_clk(0);
573 return get_usdhc_clk(1);
575 return get_usdhc_clk(2);
577 return get_usdhc_clk(3);
579 return get_ahb_clk();
588 * Dump some core clockes.
590 int do_mx6_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
593 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
594 printf("PLL_SYS %8d MHz\n", freq
/ 1000000);
595 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
596 printf("PLL_BUS %8d MHz\n", freq
/ 1000000);
597 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
598 printf("PLL_OTG %8d MHz\n", freq
/ 1000000);
599 freq
= decode_pll(PLL_ENET
, MXC_HCLK
);
600 printf("PLL_NET %8d MHz\n", freq
/ 1000000);
603 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK
) / 1000);
604 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK
) / 1000);
605 #ifdef CONFIG_MXC_SPI
606 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK
) / 1000);
608 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000);
609 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK
) / 1000);
610 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK
) / 1000);
611 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK
) / 1000);
612 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK
) / 1000);
613 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK
) / 1000);
614 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK
) / 1000);
615 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK
) / 1000);
616 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK
) / 1000);
622 void enable_ipu_clock(void)
624 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
626 reg
= readl(&mxc_ccm
->CCGR3
);
627 reg
|= MXC_CCM_CCGR3_IPU1_IPU_MASK
;
628 writel(reg
, &mxc_ccm
->CCGR3
);
631 /***************************************************/
634 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx6_showclocks
,