2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS
, /* System PLL */
18 PLL_BUS
, /* System Bus PLL*/
19 PLL_USBOTG
, /* OTG USB PLL */
20 PLL_ENET
, /* ENET PLL */
21 PLL_AUDIO
, /* AUDIO PLL */
22 PLL_VIDEO
, /* AUDIO PLL */
25 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable
)
32 reg
= __raw_readl(&imx_ccm
->CCGR2
);
34 reg
|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
36 reg
&= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
37 __raw_writel(reg
, &imx_ccm
->CCGR2
);
41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg
)
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm
->CCGR4
,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
55 clrsetbits_le32(&imx_ccm
->cs2cdr
,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
,
61 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
63 clrbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
65 clrsetbits_le32(&imx_ccm
->cs2cdr
,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
71 setbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
73 setbits_le32(&imx_ccm
->CCGR4
,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
82 void enable_usboh3_clk(unsigned char enable
)
86 reg
= __raw_readl(&imx_ccm
->CCGR6
);
88 reg
|= MXC_CCM_CCGR6_USBOH3_MASK
;
90 reg
&= ~(MXC_CCM_CCGR6_USBOH3_MASK
);
91 __raw_writel(reg
, &imx_ccm
->CCGR6
);
95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
96 void enable_enet_clk(unsigned char enable
)
100 if (is_cpu_type(MXC_CPU_MX6UL
)) {
101 mask
= MXC_CCM_CCGR3_ENET_MASK
;
102 addr
= &imx_ccm
->CCGR3
;
104 mask
= MXC_CCM_CCGR1_ENET_MASK
;
105 addr
= &imx_ccm
->CCGR1
;
109 setbits_le32(addr
, mask
);
111 clrbits_le32(addr
, mask
);
115 #ifdef CONFIG_MXC_UART
116 void enable_uart_clk(unsigned char enable
)
120 if (is_cpu_type(MXC_CPU_MX6UL
))
121 mask
= MXC_CCM_CCGR5_UART_MASK
;
123 mask
= MXC_CCM_CCGR5_UART_MASK
| MXC_CCM_CCGR5_UART_SERIAL_MASK
;
126 setbits_le32(&imx_ccm
->CCGR5
, mask
);
128 clrbits_le32(&imx_ccm
->CCGR5
, mask
);
133 int enable_usdhc_clk(unsigned char enable
, unsigned bus_num
)
140 mask
= MXC_CCM_CCGR_CG_MASK
<< (bus_num
* 2 + 2);
142 setbits_le32(&imx_ccm
->CCGR6
, mask
);
144 clrbits_le32(&imx_ccm
->CCGR6
, mask
);
150 #ifdef CONFIG_SYS_I2C_MXC
151 /* i2c_num can be from 0 - 3 */
152 int enable_i2c_clk(unsigned char enable
, unsigned i2c_num
)
161 mask
= MXC_CCM_CCGR_CG_MASK
162 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
164 reg
= __raw_readl(&imx_ccm
->CCGR2
);
169 __raw_writel(reg
, &imx_ccm
->CCGR2
);
171 if (is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
)) {
172 mask
= MXC_CCM_CCGR6_I2C4_MASK
;
173 addr
= &imx_ccm
->CCGR6
;
175 mask
= MXC_CCM_CCGR1_I2C4_SERIAL_MASK
;
176 addr
= &imx_ccm
->CCGR1
;
178 reg
= __raw_readl(addr
);
183 __raw_writel(reg
, addr
);
189 /* spi_num can be from 0 - SPI_MAX_NUM */
190 int enable_spi_clk(unsigned char enable
, unsigned spi_num
)
195 if (spi_num
> SPI_MAX_NUM
)
198 mask
= MXC_CCM_CCGR_CG_MASK
<< (spi_num
<< 1);
199 reg
= __raw_readl(&imx_ccm
->CCGR1
);
204 __raw_writel(reg
, &imx_ccm
->CCGR1
);
207 static u32
decode_pll(enum pll_clocks pll
, u32 infreq
)
209 u32 div
, test_div
, pll_num
, pll_denom
;
213 div
= __raw_readl(&imx_ccm
->analog_pll_sys
);
214 div
&= BM_ANADIG_PLL_SYS_DIV_SELECT
;
216 return (infreq
* div
) >> 1;
218 div
= __raw_readl(&imx_ccm
->analog_pll_528
);
219 div
&= BM_ANADIG_PLL_528_DIV_SELECT
;
221 return infreq
* (20 + (div
<< 1));
223 div
= __raw_readl(&imx_ccm
->analog_usb1_pll_480_ctrl
);
224 div
&= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT
;
226 return infreq
* (20 + (div
<< 1));
228 div
= __raw_readl(&imx_ccm
->analog_pll_enet
);
229 div
&= BM_ANADIG_PLL_ENET_DIV_SELECT
;
231 return 25000000 * (div
+ (div
>> 1) + 1);
233 div
= __raw_readl(&imx_ccm
->analog_pll_audio
);
234 if (!(div
& BM_ANADIG_PLL_AUDIO_ENABLE
))
236 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
237 if (div
& BM_ANADIG_PLL_AUDIO_BYPASS
)
239 pll_num
= __raw_readl(&imx_ccm
->analog_pll_audio_num
);
240 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_audio_denom
);
241 test_div
= (div
& BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
) >>
242 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
;
243 div
&= BM_ANADIG_PLL_AUDIO_DIV_SELECT
;
245 debug("Error test_div\n");
248 test_div
= 1 << (2 - test_div
);
250 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
252 div
= __raw_readl(&imx_ccm
->analog_pll_video
);
253 if (!(div
& BM_ANADIG_PLL_VIDEO_ENABLE
))
255 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
256 if (div
& BM_ANADIG_PLL_VIDEO_BYPASS
)
258 pll_num
= __raw_readl(&imx_ccm
->analog_pll_video_num
);
259 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_video_denom
);
260 test_div
= (div
& BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
) >>
261 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT
;
262 div
&= BM_ANADIG_PLL_VIDEO_DIV_SELECT
;
264 debug("Error test_div\n");
267 test_div
= 1 << (2 - test_div
);
269 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
275 static u32
mxc_get_pll_pfd(enum pll_clocks pll
, int pfd_num
)
282 if (!is_cpu_type(MXC_CPU_MX6UL
)) {
284 /* No PFD3 on PPL2 */
288 div
= __raw_readl(&imx_ccm
->analog_pfd_528
);
289 freq
= (u64
)decode_pll(PLL_BUS
, MXC_HCLK
);
292 div
= __raw_readl(&imx_ccm
->analog_pfd_480
);
293 freq
= (u64
)decode_pll(PLL_USBOTG
, MXC_HCLK
);
296 /* No PFD on other PLL */
300 return lldiv(freq
* 18, (div
& ANATOP_PFD_FRAC_MASK(pfd_num
)) >>
301 ANATOP_PFD_FRAC_SHIFT(pfd_num
));
304 static u32
get_mcu_main_clk(void)
308 reg
= __raw_readl(&imx_ccm
->cacrr
);
309 reg
&= MXC_CCM_CACRR_ARM_PODF_MASK
;
310 reg
>>= MXC_CCM_CACRR_ARM_PODF_OFFSET
;
311 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
313 return freq
/ (reg
+ 1);
316 u32
get_periph_clk(void)
318 u32 reg
, div
= 0, freq
= 0;
320 reg
= __raw_readl(&imx_ccm
->cbcdr
);
321 if (reg
& MXC_CCM_CBCDR_PERIPH_CLK_SEL
) {
322 div
= (reg
& MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK
) >>
323 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET
;
324 reg
= __raw_readl(&imx_ccm
->cbcmr
);
325 reg
&= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK
;
326 reg
>>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET
;
330 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
340 reg
= __raw_readl(&imx_ccm
->cbcmr
);
341 reg
&= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
;
342 reg
>>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
;
346 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
349 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
352 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
355 /* static / 2 divider */
356 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
363 return freq
/ (div
+ 1);
366 static u32
get_ipg_clk(void)
370 reg
= __raw_readl(&imx_ccm
->cbcdr
);
371 reg
&= MXC_CCM_CBCDR_IPG_PODF_MASK
;
372 ipg_podf
= reg
>> MXC_CCM_CBCDR_IPG_PODF_OFFSET
;
374 return get_ahb_clk() / (ipg_podf
+ 1);
377 static u32
get_ipg_per_clk(void)
379 u32 reg
, perclk_podf
;
381 reg
= __raw_readl(&imx_ccm
->cscmr1
);
382 if (is_cpu_type(MXC_CPU_MX6SL
) || is_cpu_type(MXC_CPU_MX6SX
) ||
383 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL
)) {
384 if (reg
& MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
)
385 return MXC_HCLK
; /* OSC 24Mhz */
388 perclk_podf
= reg
& MXC_CCM_CSCMR1_PERCLK_PODF_MASK
;
390 return get_ipg_clk() / (perclk_podf
+ 1);
393 static u32
get_uart_clk(void)
396 u32 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
) / 6; /* static divider */
397 reg
= __raw_readl(&imx_ccm
->cscdr1
);
399 if (is_cpu_type(MXC_CPU_MX6SL
) || is_cpu_type(MXC_CPU_MX6SX
) ||
400 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL
)) {
401 if (reg
& MXC_CCM_CSCDR1_UART_CLK_SEL
)
405 reg
&= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
;
406 uart_podf
= reg
>> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
;
408 return freq
/ (uart_podf
+ 1);
411 static u32
get_cspi_clk(void)
415 reg
= __raw_readl(&imx_ccm
->cscdr2
);
416 cspi_podf
= (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK
) >>
417 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET
;
419 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL
) ||
420 is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
)) {
421 if (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK
)
422 return MXC_HCLK
/ (cspi_podf
+ 1);
425 return decode_pll(PLL_USBOTG
, MXC_HCLK
) / (8 * (cspi_podf
+ 1));
428 static u32
get_axi_clk(void)
430 u32 root_freq
, axi_podf
;
431 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
433 axi_podf
= cbcdr
& MXC_CCM_CBCDR_AXI_PODF_MASK
;
434 axi_podf
>>= MXC_CCM_CBCDR_AXI_PODF_OFFSET
;
436 if (cbcdr
& MXC_CCM_CBCDR_AXI_SEL
) {
437 if (cbcdr
& MXC_CCM_CBCDR_AXI_ALT_SEL
)
438 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
440 root_freq
= mxc_get_pll_pfd(PLL_USBOTG
, 1);
442 root_freq
= get_periph_clk();
444 return root_freq
/ (axi_podf
+ 1);
447 static u32
get_emi_slow_clk(void)
449 u32 emi_clk_sel
, emi_slow_podf
, cscmr1
, root_freq
= 0;
451 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
452 emi_clk_sel
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK
;
453 emi_clk_sel
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET
;
454 emi_slow_podf
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK
;
455 emi_slow_podf
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET
;
457 switch (emi_clk_sel
) {
459 root_freq
= get_axi_clk();
462 root_freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
465 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
468 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
472 return root_freq
/ (emi_slow_podf
+ 1);
475 static u32
get_mmdc_ch0_clk(void)
477 u32 cbcmr
= __raw_readl(&imx_ccm
->cbcmr
);
478 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
480 u32 freq
, podf
, per2_clk2_podf
, pmu_misc2_audio_div
;
482 if (is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
) ||
483 is_cpu_type(MXC_CPU_MX6SL
)) {
484 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK
) >>
485 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET
;
486 if (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK_SEL
) {
487 per2_clk2_podf
= (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK
) >>
488 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET
;
489 if (is_cpu_type(MXC_CPU_MX6SL
)) {
490 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
493 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
495 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
496 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
498 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
503 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
) >>
504 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
) {
506 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
509 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
512 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
515 pmu_misc2_audio_div
= PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm
->pmu_misc2
));
516 switch (pmu_misc2_audio_div
) {
519 pmu_misc2_audio_div
= 1;
522 pmu_misc2_audio_div
= 2;
525 pmu_misc2_audio_div
= 4;
528 freq
= decode_pll(PLL_AUDIO
, MXC_HCLK
) /
533 return freq
/ (podf
+ 1) / (per2_clk2_podf
+ 1);
535 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK
) >>
536 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET
;
537 return get_periph_clk() / (podf
+ 1);
541 #if defined(CONFIG_VIDEO_MXS)
542 static int enable_pll_video(u32 pll_div
, u32 pll_num
, u32 pll_denom
,
548 debug("pll5 div = %d, num = %d, denom = %d\n",
549 pll_div
, pll_num
, pll_denom
);
551 /* Power up PLL5 video */
552 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN
|
553 BM_ANADIG_PLL_VIDEO_BYPASS
|
554 BM_ANADIG_PLL_VIDEO_DIV_SELECT
|
555 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
,
556 &imx_ccm
->analog_pll_video_clr
);
558 /* Set div, num and denom */
561 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
562 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
563 &imx_ccm
->analog_pll_video_set
);
566 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
567 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
568 &imx_ccm
->analog_pll_video_set
);
571 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
572 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
573 &imx_ccm
->analog_pll_video_set
);
576 puts("Wrong test_div!\n");
580 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num
),
581 &imx_ccm
->analog_pll_video_num
);
582 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom
),
583 &imx_ccm
->analog_pll_video_denom
);
586 start
= get_timer(0); /* Get current timestamp */
589 reg
= readl(&imx_ccm
->analog_pll_video
);
590 if (reg
& BM_ANADIG_PLL_VIDEO_LOCK
) {
592 writel(BM_ANADIG_PLL_VIDEO_ENABLE
,
593 &imx_ccm
->analog_pll_video_set
);
596 } while (get_timer(0) < (start
+ 10)); /* Wait 10ms */
598 puts("Lock PLL5 timeout\n");
604 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
606 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
608 void mxs_set_lcdclk(u32 base_addr
, u32 freq
)
611 u32 hck
= MXC_HCLK
/ 1000;
612 /* DIV_SELECT ranges from 27 to 54 */
616 u32 i
, j
, max_pred
= 8, max_postd
= 8, pred
= 1, postd
= 1;
617 u32 pll_div
, pll_num
, pll_denom
, post_div
= 1;
619 debug("mxs_set_lcdclk, freq = %dKHz\n", freq
);
621 if ((!is_cpu_type(MXC_CPU_MX6SX
)) && !is_cpu_type(MXC_CPU_MX6UL
)) {
622 debug("This chip not support lcd!\n");
626 if (base_addr
== LCDIF1_BASE_ADDR
) {
627 reg
= readl(&imx_ccm
->cscdr2
);
628 /* Can't change clocks when clock not from pre-mux */
629 if ((reg
& MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
) != 0)
633 if (is_cpu_type(MXC_CPU_MX6SX
)) {
634 reg
= readl(&imx_ccm
->cscdr2
);
635 /* Can't change clocks when clock not from pre-mux */
636 if ((reg
& MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
) != 0)
640 temp
= freq
* max_pred
* max_postd
;
642 puts("Please decrease freq, too large!\n");
647 * Register: PLL_VIDEO
648 * Bit Field: POST_DIV_SELECT
649 * 00 — Divide by 4.
650 * 01 — Divide by 2.
651 * 10 — Divide by 1.
653 * No need to check post_div(1)
655 for (post_div
= 2; post_div
<= 4; post_div
<<= 1) {
656 if ((temp
* post_div
) > min
) {
663 printf("Fail to set rate to %dkhz", freq
);
668 /* Choose the best pred and postd to match freq for lcd */
669 for (i
= 1; i
<= max_pred
; i
++) {
670 for (j
= 1; j
<= max_postd
; j
++) {
672 if (temp
> max
|| temp
< min
)
674 if (best
== 0 || temp
< best
) {
683 printf("Fail to set rate to %dKHz", freq
);
687 debug("best %d, pred = %d, postd = %d\n", best
, pred
, postd
);
689 pll_div
= best
/ hck
;
691 pll_num
= (best
- hck
* pll_div
) * pll_denom
/ hck
;
695 * (24MHz * (pll_div + --------- ))
697 *freq KHz = --------------------------------
698 * post_div * pred * postd * 1000
701 if (base_addr
== LCDIF1_BASE_ADDR
) {
702 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
705 /* Select pre-lcd clock to PLL5 and set pre divider */
706 clrsetbits_le32(&imx_ccm
->cscdr2
,
707 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK
|
708 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK
,
709 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET
) |
711 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET
));
713 /* Set the post divider */
714 clrsetbits_le32(&imx_ccm
->cbcmr
,
715 MXC_CCM_CBCMR_LCDIF1_PODF_MASK
,
717 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET
));
718 } else if (is_cpu_type(MXC_CPU_MX6SX
)) {
719 /* Setting LCDIF2 for i.MX6SX */
720 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
723 /* Select pre-lcd clock to PLL5 and set pre divider */
724 clrsetbits_le32(&imx_ccm
->cscdr2
,
725 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK
|
726 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK
,
727 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET
) |
729 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET
));
731 /* Set the post divider */
732 clrsetbits_le32(&imx_ccm
->cscmr1
,
733 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK
,
735 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET
));
739 int enable_lcdif_clock(u32 base_addr
)
742 u32 lcdif_clk_sel_mask
, lcdif_ccgr3_mask
;
744 if (is_cpu_type(MXC_CPU_MX6SX
)) {
745 if ((base_addr
== LCDIF1_BASE_ADDR
) ||
746 (base_addr
== LCDIF2_BASE_ADDR
)) {
747 puts("Wrong LCD interface!\n");
750 /* Set to pre-mux clock at default */
751 lcdif_clk_sel_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
752 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
:
753 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
754 lcdif_ccgr3_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
755 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK
|
756 MXC_CCM_CCGR3_DISP_AXI_MASK
) :
757 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK
|
758 MXC_CCM_CCGR3_DISP_AXI_MASK
);
759 } else if (is_cpu_type(MXC_CPU_MX6UL
)) {
760 if (base_addr
!= LCDIF1_BASE_ADDR
) {
761 puts("Wrong LCD interface!\n");
764 /* Set to pre-mux clock at default */
765 lcdif_clk_sel_mask
= MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
766 lcdif_ccgr3_mask
= MXC_CCM_CCGR3_LCDIF1_PIX_MASK
;
771 reg
= readl(&imx_ccm
->cscdr2
);
772 reg
&= ~lcdif_clk_sel_mask
;
773 writel(reg
, &imx_ccm
->cscdr2
);
775 /* Enable the LCDIF pix clock */
776 reg
= readl(&imx_ccm
->CCGR3
);
777 reg
|= lcdif_ccgr3_mask
;
778 writel(reg
, &imx_ccm
->CCGR3
);
780 reg
= readl(&imx_ccm
->CCGR2
);
781 reg
|= MXC_CCM_CCGR2_LCD_MASK
;
782 writel(reg
, &imx_ccm
->CCGR2
);
788 #ifdef CONFIG_FSL_QSPI
789 /* qspi_num can be from 0 - 1 */
790 void enable_qspi_clk(int qspi_num
)
793 /* Enable QuadSPI clock */
796 /* disable the clock gate */
797 clrbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
799 /* set 50M : (50 = 396 / 2 / 4) */
800 reg
= readl(&imx_ccm
->cscmr1
);
801 reg
&= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK
|
802 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK
);
803 reg
|= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET
) |
804 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET
));
805 writel(reg
, &imx_ccm
->cscmr1
);
807 /* enable the clock gate */
808 setbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
812 * disable the clock gate
813 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
814 * disable both of them.
816 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
817 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
819 /* set 50M : (50 = 396 / 2 / 4) */
820 reg
= readl(&imx_ccm
->cs2cdr
);
821 reg
&= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
822 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
823 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
);
824 reg
|= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
825 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
826 writel(reg
, &imx_ccm
->cs2cdr
);
828 /*enable the clock gate*/
829 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
830 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
838 #ifdef CONFIG_FEC_MXC
839 int enable_fec_anatop_clock(int fec_id
, enum enet_freq freq
)
842 s32 timeout
= 100000;
844 struct anatop_regs __iomem
*anatop
=
845 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
847 if (freq
< ENET_25MHZ
|| freq
> ENET_125MHZ
)
850 reg
= readl(&anatop
->pll_enet
);
853 reg
&= ~BM_ANADIG_PLL_ENET_DIV_SELECT
;
854 reg
|= BF_ANADIG_PLL_ENET_DIV_SELECT(freq
);
855 } else if (fec_id
== 1) {
856 /* Only i.MX6SX/UL support ENET2 */
857 if (!(is_cpu_type(MXC_CPU_MX6SX
) ||
858 is_cpu_type(MXC_CPU_MX6UL
)))
860 reg
&= ~BM_ANADIG_PLL_ENET2_DIV_SELECT
;
861 reg
|= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq
);
866 if ((reg
& BM_ANADIG_PLL_ENET_POWERDOWN
) ||
867 (!(reg
& BM_ANADIG_PLL_ENET_LOCK
))) {
868 reg
&= ~BM_ANADIG_PLL_ENET_POWERDOWN
;
869 writel(reg
, &anatop
->pll_enet
);
871 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_ENET_LOCK
)
878 /* Enable FEC clock */
880 reg
|= BM_ANADIG_PLL_ENET_ENABLE
;
882 reg
|= BM_ANADIG_PLL_ENET2_ENABLE
;
883 reg
&= ~BM_ANADIG_PLL_ENET_BYPASS
;
884 writel(reg
, &anatop
->pll_enet
);
888 * Set enet ahb clock to 200MHz
889 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
891 reg
= readl(&imx_ccm
->chsccdr
);
892 reg
&= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
893 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
894 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK
);
896 reg
|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET
);
898 reg
|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET
);
899 reg
|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET
);
900 writel(reg
, &imx_ccm
->chsccdr
);
902 /* Enable enet system clock */
903 reg
= readl(&imx_ccm
->CCGR3
);
904 reg
|= MXC_CCM_CCGR3_ENET_MASK
;
905 writel(reg
, &imx_ccm
->CCGR3
);
911 static u32
get_usdhc_clk(u32 port
)
913 u32 root_freq
= 0, usdhc_podf
= 0, clk_sel
= 0;
914 u32 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
915 u32 cscdr1
= __raw_readl(&imx_ccm
->cscdr1
);
919 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC1_PODF_MASK
) >>
920 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET
;
921 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC1_CLK_SEL
;
925 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC2_PODF_MASK
) >>
926 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET
;
927 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC2_CLK_SEL
;
931 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC3_PODF_MASK
) >>
932 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET
;
933 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC3_CLK_SEL
;
937 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC4_PODF_MASK
) >>
938 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET
;
939 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC4_CLK_SEL
;
947 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
949 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
951 return root_freq
/ (usdhc_podf
+ 1);
954 u32
imx_get_uartclk(void)
956 return get_uart_clk();
959 u32
imx_get_fecclk(void)
961 return mxc_get_clock(MXC_IPG_CLK
);
964 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
965 static int enable_enet_pll(uint32_t en
)
967 struct mxc_ccm_reg
*const imx_ccm
968 = (struct mxc_ccm_reg
*) CCM_BASE_ADDR
;
969 s32 timeout
= 100000;
973 reg
= readl(&imx_ccm
->analog_pll_enet
);
974 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
975 writel(reg
, &imx_ccm
->analog_pll_enet
);
976 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
978 if (readl(&imx_ccm
->analog_pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
983 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
984 writel(reg
, &imx_ccm
->analog_pll_enet
);
986 writel(reg
, &imx_ccm
->analog_pll_enet
);
991 #ifdef CONFIG_CMD_SATA
992 static void ungate_sata_clock(void)
994 struct mxc_ccm_reg
*const imx_ccm
=
995 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
997 /* Enable SATA clock. */
998 setbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1001 int enable_sata_clock(void)
1003 ungate_sata_clock();
1004 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
);
1007 void disable_sata_clock(void)
1009 struct mxc_ccm_reg
*const imx_ccm
=
1010 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1012 clrbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1016 #ifdef CONFIG_PCIE_IMX
1017 static void ungate_pcie_clock(void)
1019 struct mxc_ccm_reg
*const imx_ccm
=
1020 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1022 /* Enable PCIe clock. */
1023 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_PCIE_MASK
);
1026 int enable_pcie_clock(void)
1028 struct anatop_regs
*anatop_regs
=
1029 (struct anatop_regs
*)ANATOP_BASE_ADDR
;
1030 struct mxc_ccm_reg
*ccm_regs
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1036 * The register ANATOP_MISC1 is not documented in the Freescale
1037 * MX6RM. The register that is mapped in the ANATOP space and
1038 * marked as ANATOP_MISC1 is actually documented in the PMU section
1039 * of the datasheet as PMU_MISC1.
1041 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1042 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1043 * for PCI express link that is clocked from the i.MX6.
1045 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1046 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1047 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1048 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1049 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1051 if (is_cpu_type(MXC_CPU_MX6SX
))
1052 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF
;
1054 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF
;
1056 clrsetbits_le32(&anatop_regs
->ana_misc1
,
1057 ANADIG_ANA_MISC1_LVDSCLK1_IBEN
|
1058 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK
,
1059 ANADIG_ANA_MISC1_LVDSCLK1_OBEN
| lvds1_clk_sel
);
1061 /* PCIe reference clock sourced from AXI. */
1062 clrbits_le32(&ccm_regs
->cbcmr
, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL
);
1064 /* Party time! Ungate the clock to the PCIe. */
1065 #ifdef CONFIG_CMD_SATA
1066 ungate_sata_clock();
1068 ungate_pcie_clock();
1070 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
|
1071 BM_ANADIG_PLL_ENET_ENABLE_PCIE
);
1075 #ifdef CONFIG_SECURE_BOOT
1076 void hab_caam_clock_enable(unsigned char enable
)
1080 /* CG4 ~ CG6, CAAM clocks */
1081 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1083 reg
|= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1084 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1085 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1087 reg
&= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1088 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1089 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1090 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1093 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1095 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1097 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1098 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1102 static void enable_pll3(void)
1104 struct anatop_regs __iomem
*anatop
=
1105 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
1107 /* make sure pll3 is enabled */
1108 if ((readl(&anatop
->usb1_pll_480_ctrl
) &
1109 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0) {
1110 /* enable pll's power */
1111 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER
,
1112 &anatop
->usb1_pll_480_ctrl_set
);
1113 writel(0x80, &anatop
->ana_misc2_clr
);
1114 /* wait for pll lock */
1115 while ((readl(&anatop
->usb1_pll_480_ctrl
) &
1116 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0)
1118 /* disable bypass */
1119 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS
,
1120 &anatop
->usb1_pll_480_ctrl_clr
);
1121 /* enable pll output */
1122 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE
,
1123 &anatop
->usb1_pll_480_ctrl_set
);
1127 void enable_thermal_clk(void)
1132 unsigned int mxc_get_clock(enum mxc_clock clk
)
1136 return get_mcu_main_clk();
1138 return get_periph_clk();
1140 return get_ahb_clk();
1142 return get_ipg_clk();
1143 case MXC_IPG_PERCLK
:
1145 return get_ipg_per_clk();
1147 return get_uart_clk();
1149 return get_cspi_clk();
1151 return get_axi_clk();
1152 case MXC_EMI_SLOW_CLK
:
1153 return get_emi_slow_clk();
1155 return get_mmdc_ch0_clk();
1157 return get_usdhc_clk(0);
1158 case MXC_ESDHC2_CLK
:
1159 return get_usdhc_clk(1);
1160 case MXC_ESDHC3_CLK
:
1161 return get_usdhc_clk(2);
1162 case MXC_ESDHC4_CLK
:
1163 return get_usdhc_clk(3);
1165 return get_ahb_clk();
1167 printf("Unsupported MXC CLK: %d\n", clk
);
1175 * Dump some core clockes.
1177 int do_mx6_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
1180 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
1181 printf("PLL_SYS %8d MHz\n", freq
/ 1000000);
1182 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
1183 printf("PLL_BUS %8d MHz\n", freq
/ 1000000);
1184 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
1185 printf("PLL_OTG %8d MHz\n", freq
/ 1000000);
1186 freq
= decode_pll(PLL_ENET
, MXC_HCLK
);
1187 printf("PLL_NET %8d MHz\n", freq
/ 1000000);
1190 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK
) / 1000);
1191 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK
) / 1000);
1192 #ifdef CONFIG_MXC_SPI
1193 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK
) / 1000);
1195 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000);
1196 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK
) / 1000);
1197 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK
) / 1000);
1198 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK
) / 1000);
1199 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK
) / 1000);
1200 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK
) / 1000);
1201 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK
) / 1000);
1202 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK
) / 1000);
1203 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK
) / 1000);
1208 #ifndef CONFIG_MX6SX
1209 void enable_ipu_clock(void)
1211 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1213 reg
= readl(&mxc_ccm
->CCGR3
);
1214 reg
|= MXC_CCM_CCGR3_IPU1_IPU_MASK
;
1215 writel(reg
, &mxc_ccm
->CCGR3
);
1218 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_PRG_CLK0_MASK
);
1219 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_IPU2_IPU_MASK
);
1223 /***************************************************/
1226 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx6_showclocks
,