arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21 };
  22
  23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  24
  25 #ifdef CONFIG_MXC_OCOTP
  26 void enable_ocotp_clk(unsigned char enable)
  27 {
  28         u32 reg;
  29
  30         reg = __raw_readl(&imx_ccm->CCGR2);
  31         if (enable)
  32                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  33         else
  34                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         __raw_writel(reg, &imx_ccm->CCGR2);
  36 }
  37 #endif
  38
  39 #ifdef CONFIG_NAND_MXS
  40 void setup_gpmi_io_clk(u32 cfg)
  41 {
  42         /* Disable clocks per ERR007177 from MX6 errata */
  43         clrbits_le32(&imx_ccm->CCGR4,
  44                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  45                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  46                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  48                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  49
  50         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  51
  52         clrsetbits_le32(&imx_ccm->cs2cdr,
  53                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  54                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  55                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  56                         cfg);
  57
  58         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  59         setbits_le32(&imx_ccm->CCGR4,
  60                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65 }
  66 #endif
  67
  68 void enable_usboh3_clk(unsigned char enable)
  69 {
  70         u32 reg;
  71
  72         reg = __raw_readl(&imx_ccm->CCGR6);
  73         if (enable)
  74                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  75         else
  76                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  77         __raw_writel(reg, &imx_ccm->CCGR6);
  78
  79 }
  80
  81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  82 void enable_enet_clk(unsigned char enable)
  83 {
  84         u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
  85
  86         if (enable)
  87                 setbits_le32(&imx_ccm->CCGR1, mask);
  88         else
  89                 clrbits_le32(&imx_ccm->CCGR1, mask);
  90 }
  91 #endif
  92
  93 #ifdef CONFIG_MXC_UART
  94 void enable_uart_clk(unsigned char enable)
  95 {
  96         u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
  97
  98         if (enable)
  99                 setbits_le32(&imx_ccm->CCGR5, mask);
 100         else
 101                 clrbits_le32(&imx_ccm->CCGR5, mask);
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_SPI
 106 /* spi_num can be from 0 - 4 */
 107 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
 108 {
 109         u32 mask;
 110
 111         if (spi_num > 4)
 112                 return -EINVAL;
 113
 114         mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
 115         if (enable)
 116                 setbits_le32(&imx_ccm->CCGR1, mask);
 117         else
 118                 clrbits_le32(&imx_ccm->CCGR1, mask);
 119
 120         return 0;
 121 }
 122 #endif
 123
 124 #ifdef CONFIG_MMC
 125 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 126 {
 127         u32 mask;
 128
 129         if (bus_num > 3)
 130                 return -EINVAL;
 131
 132         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 133         if (enable)
 134                 setbits_le32(&imx_ccm->CCGR6, mask);
 135         else
 136                 clrbits_le32(&imx_ccm->CCGR6, mask);
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_SYS_I2C_MXC
 143 /* i2c_num can be from 0 - 3 */
 144 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 145 {
 146         u32 reg;
 147         u32 mask;
 148
 149         if (i2c_num > 3)
 150                 return -EINVAL;
 151         if (i2c_num < 3) {
 152                 mask = MXC_CCM_CCGR_CG_MASK
 153                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 154                         + (i2c_num << 1));
 155                 reg = __raw_readl(&imx_ccm->CCGR2);
 156                 if (enable)
 157                         reg |= mask;
 158                 else
 159                         reg &= ~mask;
 160                 __raw_writel(reg, &imx_ccm->CCGR2);
 161         } else {
 162                 mask = MXC_CCM_CCGR_CG_MASK
 163                         << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
 164                 reg = __raw_readl(&imx_ccm->CCGR1);
 165                 if (enable)
 166                         reg |= mask;
 167                 else
 168                         reg &= ~mask;
 169                 __raw_writel(reg, &imx_ccm->CCGR1);
 170         }
 171         return 0;
 172 }
 173 #endif
 174
 175 /* spi_num can be from 0 - SPI_MAX_NUM */
 176 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 177 {
 178         u32 reg;
 179         u32 mask;
 180
 181         if (spi_num > SPI_MAX_NUM)
 182                 return -EINVAL;
 183
 184         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 185         reg = __raw_readl(&imx_ccm->CCGR1);
 186         if (enable)
 187                 reg |= mask;
 188         else
 189                 reg &= ~mask;
 190         __raw_writel(reg, &imx_ccm->CCGR1);
 191         return 0;
 192 }
 193 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 194 {
 195         u32 div;
 196
 197         switch (pll) {
 198         case PLL_SYS:
 199                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 200                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 201
 202                 return (infreq * div) >> 1;
 203         case PLL_BUS:
 204                 div = __raw_readl(&imx_ccm->analog_pll_528);
 205                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 206
 207                 return infreq * (20 + (div << 1));
 208         case PLL_USBOTG:
 209                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 210                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 211
 212                 return infreq * (20 + (div << 1));
 213         case PLL_ENET:
 214                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 215                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 216
 217                 return 25000000 * (div + (div >> 1) + 1);
 218         default:
 219                 return 0;
 220         }
 221         /* NOTREACHED */
 222 }
 223 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 224 {
 225         u32 div;
 226         u64 freq;
 227
 228         switch (pll) {
 229         case PLL_BUS:
 230                 if (pfd_num == 3) {
 231                         /* No PFD3 on PPL2 */
 232                         return 0;
 233                 }
 234                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 235                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 236                 break;
 237         case PLL_USBOTG:
 238                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 239                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 240                 break;
 241         default:
 242                 /* No PFD on other PLL                                       */
 243                 return 0;
 244         }
 245
 246         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 247                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 248 }
 249
 250 static u32 get_mcu_main_clk(void)
 251 {
 252         u32 reg, freq;
 253
 254         reg = __raw_readl(&imx_ccm->cacrr);
 255         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 256         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 257         freq = decode_pll(PLL_SYS, MXC_HCLK);
 258
 259         return freq / (reg + 1);
 260 }
 261
 262 u32 get_periph_clk(void)
 263 {
 264         u32 reg, freq = 0;
 265
 266         reg = __raw_readl(&imx_ccm->cbcdr);
 267         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 268                 reg = __raw_readl(&imx_ccm->cbcmr);
 269                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 270                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 271
 272                 switch (reg) {
 273                 case 0:
 274                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 275                         break;
 276                 case 1:
 277                 case 2:
 278                         freq = MXC_HCLK;
 279                         break;
 280                 default:
 281                         break;
 282                 }
 283         } else {
 284                 reg = __raw_readl(&imx_ccm->cbcmr);
 285                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 286                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 287
 288                 switch (reg) {
 289                 case 0:
 290                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 291                         break;
 292                 case 1:
 293                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 294                         break;
 295                 case 2:
 296                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 297                         break;
 298                 case 3:
 299                         /* static / 2 divider */
 300                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 301                         break;
 302                 default:
 303                         break;
 304                 }
 305         }
 306
 307         return freq;
 308 }
 309
 310 static u32 get_ipg_clk(void)
 311 {
 312         u32 reg, ipg_podf;
 313
 314         reg = __raw_readl(&imx_ccm->cbcdr);
 315         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 316         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 317
 318         return get_ahb_clk() / (ipg_podf + 1);
 319 }
 320
 321 static u32 get_ipg_per_clk(void)
 322 {
 323         u32 reg, perclk_podf;
 324
 325         reg = __raw_readl(&imx_ccm->cscmr1);
 326 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 327         if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 328                 return MXC_HCLK; /* OSC 24Mhz */
 329 #endif
 330         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 331
 332         return get_ipg_clk() / (perclk_podf + 1);
 333 }
 334
 335 static u32 get_uart_clk(void)
 336 {
 337         u32 reg, uart_podf;
 338         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 339         reg = __raw_readl(&imx_ccm->cscdr1);
 340 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 341         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 342                 freq = MXC_HCLK;
 343 #endif
 344         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 345         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 346
 347         return freq / (uart_podf + 1);
 348 }
 349
 350 static u32 get_cspi_clk(void)
 351 {
 352         u32 reg, cspi_podf;
 353
 354         reg = __raw_readl(&imx_ccm->cscdr2);
 355         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 356         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 357
 358         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 359 }
 360
 361 static u32 get_axi_clk(void)
 362 {
 363         u32 root_freq, axi_podf;
 364         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 365
 366         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 367         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 368
 369         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 370                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 371                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 372                 else
 373                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 374         } else
 375                 root_freq = get_periph_clk();
 376
 377         return  root_freq / (axi_podf + 1);
 378 }
 379
 380 static u32 get_emi_slow_clk(void)
 381 {
 382         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 383
 384         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 385         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 386         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 387         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 388         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 389
 390         switch (emi_clk_sel) {
 391         case 0:
 392                 root_freq = get_axi_clk();
 393                 break;
 394         case 1:
 395                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 396                 break;
 397         case 2:
 398                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 399                 break;
 400         case 3:
 401                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 402                 break;
 403         }
 404
 405         return root_freq / (emi_slow_podf + 1);
 406 }
 407
 408 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 409 static u32 get_mmdc_ch0_clk(void)
 410 {
 411         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 412         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 413         u32 freq, podf;
 414
 415         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
 416                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 417
 418         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 419                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 420         case 0:
 421                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 422                 break;
 423         case 1:
 424                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 425                 break;
 426         case 2:
 427                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 428                 break;
 429         case 3:
 430                 /* static / 2 divider */
 431                 freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 432         }
 433
 434         return freq / (podf + 1);
 435
 436 }
 437 #else
 438 static u32 get_mmdc_ch0_clk(void)
 439 {
 440         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 441         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 442                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 443
 444         return get_periph_clk() / (mmdc_ch0_podf + 1);
 445 }
 446 #endif
 447
 448 #ifdef CONFIG_MX6SX
 449 /* qspi_num can be from 0 - 1 */
 450 void enable_qspi_clk(int qspi_num)
 451 {
 452         u32 reg = 0;
 453         /* Enable QuadSPI clock */
 454         switch (qspi_num) {
 455         case 0:
 456                 /* disable the clock gate */
 457                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 458
 459                 /* set 50M  : (50 = 396 / 2 / 4) */
 460                 reg = readl(&imx_ccm->cscmr1);
 461                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 462                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 463                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 464                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 465                 writel(reg, &imx_ccm->cscmr1);
 466
 467                 /* enable the clock gate */
 468                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 469                 break;
 470         case 1:
 471                 /*
 472                  * disable the clock gate
 473                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 474                  * disable both of them.
 475                  */
 476                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 477                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 478
 479                 /* set 50M  : (50 = 396 / 2 / 4) */
 480                 reg = readl(&imx_ccm->cs2cdr);
 481                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 482                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 483                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 484                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 485                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 486                 writel(reg, &imx_ccm->cs2cdr);
 487
 488                 /*enable the clock gate*/
 489                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 490                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 491                 break;
 492         default:
 493                 break;
 494         }
 495 }
 496 #endif
 497
 498 #ifdef CONFIG_FEC_MXC
 499 int enable_fec_anatop_clock(enum enet_freq freq)
 500 {
 501         u32 reg = 0;
 502         s32 timeout = 100000;
 503
 504         struct anatop_regs __iomem *anatop =
 505                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 506
 507         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 508                 return -EINVAL;
 509
 510         reg = readl(&anatop->pll_enet);
 511         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 512         reg |= freq;
 513
 514         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 515             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 516                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 517                 writel(reg, &anatop->pll_enet);
 518                 while (timeout--) {
 519                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 520                                 break;
 521                 }
 522                 if (timeout < 0)
 523                         return -ETIMEDOUT;
 524         }
 525
 526         /* Enable FEC clock */
 527         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 528         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 529         writel(reg, &anatop->pll_enet);
 530
 531 #ifdef CONFIG_MX6SX
 532         /*
 533          * Set enet ahb clock to 200MHz
 534          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 535          */
 536         reg = readl(&imx_ccm->chsccdr);
 537         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 538                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 539                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 540         /* PLL2 PFD2 */
 541         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 542         /* Div = 2*/
 543         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 544         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 545         writel(reg, &imx_ccm->chsccdr);
 546
 547         /* Enable enet system clock */
 548         reg = readl(&imx_ccm->CCGR3);
 549         reg |= MXC_CCM_CCGR3_ENET_MASK;
 550         writel(reg, &imx_ccm->CCGR3);
 551 #endif
 552         return 0;
 553 }
 554 #endif
 555
 556 static u32 get_usdhc_clk(u32 port)
 557 {
 558         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 559         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 560         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 561
 562         switch (port) {
 563         case 0:
 564                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 565                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 566                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 567
 568                 break;
 569         case 1:
 570                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 571                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 572                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 573
 574                 break;
 575         case 2:
 576                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 577                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 578                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 579
 580                 break;
 581         case 3:
 582                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 583                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 584                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 585
 586                 break;
 587         default:
 588                 break;
 589         }
 590
 591         if (clk_sel)
 592                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 593         else
 594                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 595
 596         return root_freq / (usdhc_podf + 1);
 597 }
 598
 599 u32 imx_get_uartclk(void)
 600 {
 601         return get_uart_clk();
 602 }
 603
 604 u32 imx_get_fecclk(void)
 605 {
 606         return mxc_get_clock(MXC_IPG_CLK);
 607 }
 608
 609 static int enable_enet_pll(uint32_t en)
 610 {
 611         struct mxc_ccm_reg *const imx_ccm
 612                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 613         s32 timeout = 100000;
 614         u32 reg = 0;
 615
 616         /* Enable PLLs */
 617         reg = readl(&imx_ccm->analog_pll_enet);
 618         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 619         writel(reg, &imx_ccm->analog_pll_enet);
 620         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 621         while (timeout--) {
 622                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 623                         break;
 624         }
 625         if (timeout <= 0)
 626                 return -EIO;
 627         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 628         writel(reg, &imx_ccm->analog_pll_enet);
 629         reg |= en;
 630         writel(reg, &imx_ccm->analog_pll_enet);
 631         return 0;
 632 }
 633
 634 #ifndef CONFIG_MX6SX
 635 static void ungate_sata_clock(void)
 636 {
 637         struct mxc_ccm_reg *const imx_ccm =
 638                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 639
 640         /* Enable SATA clock. */
 641         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 642 }
 643 #endif
 644
 645 static void ungate_pcie_clock(void)
 646 {
 647         struct mxc_ccm_reg *const imx_ccm =
 648                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 649
 650         /* Enable PCIe clock. */
 651         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 652 }
 653
 654 #ifndef CONFIG_MX6SX
 655 int enable_sata_clock(void)
 656 {
 657         ungate_sata_clock();
 658         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 659 }
 660
 661 void disable_sata_clock(void)
 662 {
 663         struct mxc_ccm_reg *const imx_ccm =
 664                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 665
 666         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 667 }
 668 #endif
 669
 670 int enable_pcie_clock(void)
 671 {
 672         struct anatop_regs *anatop_regs =
 673                 (struct anatop_regs *)ANATOP_BASE_ADDR;
 674         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 675         u32 lvds1_clk_sel;
 676
 677         /*
 678          * Here be dragons!
 679          *
 680          * The register ANATOP_MISC1 is not documented in the Freescale
 681          * MX6RM. The register that is mapped in the ANATOP space and
 682          * marked as ANATOP_MISC1 is actually documented in the PMU section
 683          * of the datasheet as PMU_MISC1.
 684          *
 685          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 686          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 687          * for PCI express link that is clocked from the i.MX6.
 688          */
 689 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 690 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 691 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 692 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 693 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 694
 695         if (is_cpu_type(MXC_CPU_MX6SX))
 696                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 697         else
 698                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 699
 700         clrsetbits_le32(&anatop_regs->ana_misc1,
 701                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 702                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 703                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 704
 705         /* PCIe reference clock sourced from AXI. */
 706         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 707
 708         /* Party time! Ungate the clock to the PCIe. */
 709 #ifndef CONFIG_MX6SX
 710         ungate_sata_clock();
 711 #endif
 712         ungate_pcie_clock();
 713
 714         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 715                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 716 }
 717
 718 #ifdef CONFIG_SECURE_BOOT
 719 void hab_caam_clock_enable(unsigned char enable)
 720 {
 721         u32 reg;
 722
 723         /* CG4 ~ CG6, CAAM clocks */
 724         reg = __raw_readl(&imx_ccm->CCGR0);
 725         if (enable)
 726                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 727                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 728                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 729         else
 730                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 731                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 732                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 733         __raw_writel(reg, &imx_ccm->CCGR0);
 734
 735         /* EMI slow clk */
 736         reg = __raw_readl(&imx_ccm->CCGR6);
 737         if (enable)
 738                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 739         else
 740                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 741         __raw_writel(reg, &imx_ccm->CCGR6);
 742 }
 743 #endif
 744
 745 static void enable_pll3(void)
 746 {
 747         struct anatop_regs __iomem *anatop =
 748                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 749
 750         /* make sure pll3 is enabled */
 751         if ((readl(&anatop->usb1_pll_480_ctrl) &
 752                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
 753                 /* enable pll's power */
 754                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
 755                        &anatop->usb1_pll_480_ctrl_set);
 756                 writel(0x80, &anatop->ana_misc2_clr);
 757                 /* wait for pll lock */
 758                 while ((readl(&anatop->usb1_pll_480_ctrl) &
 759                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
 760                         ;
 761                 /* disable bypass */
 762                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
 763                        &anatop->usb1_pll_480_ctrl_clr);
 764                 /* enable pll output */
 765                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
 766                        &anatop->usb1_pll_480_ctrl_set);
 767         }
 768 }
 769
 770 void enable_thermal_clk(void)
 771 {
 772         enable_pll3();
 773 }
 774
 775 unsigned int mxc_get_clock(enum mxc_clock clk)
 776 {
 777         switch (clk) {
 778         case MXC_ARM_CLK:
 779                 return get_mcu_main_clk();
 780         case MXC_PER_CLK:
 781                 return get_periph_clk();
 782         case MXC_AHB_CLK:
 783                 return get_ahb_clk();
 784         case MXC_IPG_CLK:
 785                 return get_ipg_clk();
 786         case MXC_IPG_PERCLK:
 787         case MXC_I2C_CLK:
 788                 return get_ipg_per_clk();
 789         case MXC_UART_CLK:
 790                 return get_uart_clk();
 791         case MXC_CSPI_CLK:
 792                 return get_cspi_clk();
 793         case MXC_AXI_CLK:
 794                 return get_axi_clk();
 795         case MXC_EMI_SLOW_CLK:
 796                 return get_emi_slow_clk();
 797         case MXC_DDR_CLK:
 798                 return get_mmdc_ch0_clk();
 799         case MXC_ESDHC_CLK:
 800                 return get_usdhc_clk(0);
 801         case MXC_ESDHC2_CLK:
 802                 return get_usdhc_clk(1);
 803         case MXC_ESDHC3_CLK:
 804                 return get_usdhc_clk(2);
 805         case MXC_ESDHC4_CLK:
 806                 return get_usdhc_clk(3);
 807         case MXC_SATA_CLK:
 808                 return get_ahb_clk();
 809         default:
 810                 printf("Unsupported MXC CLK: %d\n", clk);
 811                 break;
 812         }
 813
 814         return 0;
 815 }
 816
 817 /*
 818  * Dump some core clockes.
 819  */
 820 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 821 {
 822         u32 freq;
 823         freq = decode_pll(PLL_SYS, MXC_HCLK);
 824         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
 825         freq = decode_pll(PLL_BUS, MXC_HCLK);
 826         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
 827         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 828         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
 829         freq = decode_pll(PLL_ENET, MXC_HCLK);
 830         printf("PLL_NET    %8d MHz\n", freq / 1000000);
 831
 832         printf("\n");
 833         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 834         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 835 #ifdef CONFIG_MXC_SPI
 836         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 837 #endif
 838         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 839         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
 840         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 841         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
 842         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
 843         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 844         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
 845         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
 846         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 847
 848         return 0;
 849 }
 850
 851 #ifndef CONFIG_MX6SX
 852 void enable_ipu_clock(void)
 853 {
 854         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 855         int reg;
 856         reg = readl(&mxc_ccm->CCGR3);
 857         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 858         writel(reg, &mxc_ccm->CCGR3);
 859 }
 860 #endif
 861 /***************************************************/
 862
 863 U_BOOT_CMD(
 864         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
 865         "display clocks",
 866         ""
 867 );