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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
21 };
22
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
24
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
27 {
28 u32 reg;
29
30 reg = __raw_readl(&imx_ccm->CCGR2);
31 if (enable)
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
33 else
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
36 }
37 #endif
38
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
41 {
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
49
50 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
51
52 clrsetbits_le32(&imx_ccm->cs2cdr,
53 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
54 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
55 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
56 cfg);
57
58 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 setbits_le32(&imx_ccm->CCGR4,
60 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
65 }
66 #endif
67
68 void enable_usboh3_clk(unsigned char enable)
69 {
70 u32 reg;
71
72 reg = __raw_readl(&imx_ccm->CCGR6);
73 if (enable)
74 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
75 else
76 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
77 __raw_writel(reg, &imx_ccm->CCGR6);
78
79 }
80
81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
82 void enable_enet_clk(unsigned char enable)
83 {
84 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
85
86 if (enable)
87 setbits_le32(&imx_ccm->CCGR1, mask);
88 else
89 clrbits_le32(&imx_ccm->CCGR1, mask);
90 }
91 #endif
92
93 #ifdef CONFIG_MXC_UART
94 void enable_uart_clk(unsigned char enable)
95 {
96 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
97
98 if (enable)
99 setbits_le32(&imx_ccm->CCGR5, mask);
100 else
101 clrbits_le32(&imx_ccm->CCGR5, mask);
102 }
103 #endif
104
105 #ifdef CONFIG_SPI
106 /* spi_num can be from 0 - 4 */
107 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
108 {
109 u32 mask;
110
111 if (spi_num > 4)
112 return -EINVAL;
113
114 mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
115 if (enable)
116 setbits_le32(&imx_ccm->CCGR1, mask);
117 else
118 clrbits_le32(&imx_ccm->CCGR1, mask);
119
120 return 0;
121 }
122 #endif
123
124 #ifdef CONFIG_MMC
125 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
126 {
127 u32 mask;
128
129 if (bus_num > 3)
130 return -EINVAL;
131
132 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
133 if (enable)
134 setbits_le32(&imx_ccm->CCGR6, mask);
135 else
136 clrbits_le32(&imx_ccm->CCGR6, mask);
137
138 return 0;
139 }
140 #endif
141
142 #ifdef CONFIG_SYS_I2C_MXC
143 /* i2c_num can be from 0 - 2 */
144 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
145 {
146 u32 reg;
147 u32 mask;
148
149 if (i2c_num > 2)
150 return -EINVAL;
151
152 mask = MXC_CCM_CCGR_CG_MASK
153 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
154 reg = __raw_readl(&imx_ccm->CCGR2);
155 if (enable)
156 reg |= mask;
157 else
158 reg &= ~mask;
159 __raw_writel(reg, &imx_ccm->CCGR2);
160 return 0;
161 }
162 #endif
163
164 /* spi_num can be from 0 - SPI_MAX_NUM */
165 int enable_spi_clk(unsigned char enable, unsigned spi_num)
166 {
167 u32 reg;
168 u32 mask;
169
170 if (spi_num > SPI_MAX_NUM)
171 return -EINVAL;
172
173 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
174 reg = __raw_readl(&imx_ccm->CCGR1);
175 if (enable)
176 reg |= mask;
177 else
178 reg &= ~mask;
179 __raw_writel(reg, &imx_ccm->CCGR1);
180 return 0;
181 }
182 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
183 {
184 u32 div;
185
186 switch (pll) {
187 case PLL_SYS:
188 div = __raw_readl(&imx_ccm->analog_pll_sys);
189 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
190
191 return (infreq * div) >> 1;
192 case PLL_BUS:
193 div = __raw_readl(&imx_ccm->analog_pll_528);
194 div &= BM_ANADIG_PLL_528_DIV_SELECT;
195
196 return infreq * (20 + (div << 1));
197 case PLL_USBOTG:
198 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
199 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
200
201 return infreq * (20 + (div << 1));
202 case PLL_ENET:
203 div = __raw_readl(&imx_ccm->analog_pll_enet);
204 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
205
206 return 25000000 * (div + (div >> 1) + 1);
207 default:
208 return 0;
209 }
210 /* NOTREACHED */
211 }
212 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
213 {
214 u32 div;
215 u64 freq;
216
217 switch (pll) {
218 case PLL_BUS:
219 if (pfd_num == 3) {
220 /* No PFD3 on PPL2 */
221 return 0;
222 }
223 div = __raw_readl(&imx_ccm->analog_pfd_528);
224 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
225 break;
226 case PLL_USBOTG:
227 div = __raw_readl(&imx_ccm->analog_pfd_480);
228 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
229 break;
230 default:
231 /* No PFD on other PLL */
232 return 0;
233 }
234
235 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
236 ANATOP_PFD_FRAC_SHIFT(pfd_num));
237 }
238
239 static u32 get_mcu_main_clk(void)
240 {
241 u32 reg, freq;
242
243 reg = __raw_readl(&imx_ccm->cacrr);
244 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
245 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
246 freq = decode_pll(PLL_SYS, MXC_HCLK);
247
248 return freq / (reg + 1);
249 }
250
251 u32 get_periph_clk(void)
252 {
253 u32 reg, freq = 0;
254
255 reg = __raw_readl(&imx_ccm->cbcdr);
256 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
257 reg = __raw_readl(&imx_ccm->cbcmr);
258 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
259 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
260
261 switch (reg) {
262 case 0:
263 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
264 break;
265 case 1:
266 case 2:
267 freq = MXC_HCLK;
268 break;
269 default:
270 break;
271 }
272 } else {
273 reg = __raw_readl(&imx_ccm->cbcmr);
274 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
275 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
276
277 switch (reg) {
278 case 0:
279 freq = decode_pll(PLL_BUS, MXC_HCLK);
280 break;
281 case 1:
282 freq = mxc_get_pll_pfd(PLL_BUS, 2);
283 break;
284 case 2:
285 freq = mxc_get_pll_pfd(PLL_BUS, 0);
286 break;
287 case 3:
288 /* static / 2 divider */
289 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
290 break;
291 default:
292 break;
293 }
294 }
295
296 return freq;
297 }
298
299 static u32 get_ipg_clk(void)
300 {
301 u32 reg, ipg_podf;
302
303 reg = __raw_readl(&imx_ccm->cbcdr);
304 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
305 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
306
307 return get_ahb_clk() / (ipg_podf + 1);
308 }
309
310 static u32 get_ipg_per_clk(void)
311 {
312 u32 reg, perclk_podf;
313
314 reg = __raw_readl(&imx_ccm->cscmr1);
315 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
316
317 return get_ipg_clk() / (perclk_podf + 1);
318 }
319
320 static u32 get_uart_clk(void)
321 {
322 u32 reg, uart_podf;
323 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
324 reg = __raw_readl(&imx_ccm->cscdr1);
325 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
326 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
327 freq = MXC_HCLK;
328 #endif
329 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
330 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
331
332 return freq / (uart_podf + 1);
333 }
334
335 static u32 get_cspi_clk(void)
336 {
337 u32 reg, cspi_podf;
338
339 reg = __raw_readl(&imx_ccm->cscdr2);
340 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
341 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
342
343 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
344 }
345
346 static u32 get_axi_clk(void)
347 {
348 u32 root_freq, axi_podf;
349 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
350
351 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
352 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
353
354 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
355 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
356 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
357 else
358 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
359 } else
360 root_freq = get_periph_clk();
361
362 return root_freq / (axi_podf + 1);
363 }
364
365 static u32 get_emi_slow_clk(void)
366 {
367 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
368
369 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
370 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
371 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
372 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
373 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
374
375 switch (emi_clk_sel) {
376 case 0:
377 root_freq = get_axi_clk();
378 break;
379 case 1:
380 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
381 break;
382 case 2:
383 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
384 break;
385 case 3:
386 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
387 break;
388 }
389
390 return root_freq / (emi_slow_podf + 1);
391 }
392
393 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
394 static u32 get_mmdc_ch0_clk(void)
395 {
396 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
397 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
398 u32 freq, podf;
399
400 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
401 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
402
403 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
404 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
405 case 0:
406 freq = decode_pll(PLL_BUS, MXC_HCLK);
407 break;
408 case 1:
409 freq = mxc_get_pll_pfd(PLL_BUS, 2);
410 break;
411 case 2:
412 freq = mxc_get_pll_pfd(PLL_BUS, 0);
413 break;
414 case 3:
415 /* static / 2 divider */
416 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
417 }
418
419 return freq / (podf + 1);
420
421 }
422 #else
423 static u32 get_mmdc_ch0_clk(void)
424 {
425 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
426 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
427 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
428
429 return get_periph_clk() / (mmdc_ch0_podf + 1);
430 }
431 #endif
432
433 #ifdef CONFIG_FEC_MXC
434 int enable_fec_anatop_clock(enum enet_freq freq)
435 {
436 u32 reg = 0;
437 s32 timeout = 100000;
438
439 struct anatop_regs __iomem *anatop =
440 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
441
442 if (freq < ENET_25MHz || freq > ENET_125MHz)
443 return -EINVAL;
444
445 reg = readl(&anatop->pll_enet);
446 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
447 reg |= freq;
448
449 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
450 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
451 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
452 writel(reg, &anatop->pll_enet);
453 while (timeout--) {
454 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
455 break;
456 }
457 if (timeout < 0)
458 return -ETIMEDOUT;
459 }
460
461 /* Enable FEC clock */
462 reg |= BM_ANADIG_PLL_ENET_ENABLE;
463 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
464 writel(reg, &anatop->pll_enet);
465
466 #ifdef CONFIG_MX6SX
467 /*
468 * Set enet ahb clock to 200MHz
469 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
470 */
471 reg = readl(&imx_ccm->chsccdr);
472 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
473 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
474 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
475 /* PLL2 PFD2 */
476 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
477 /* Div = 2*/
478 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
479 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
480 writel(reg, &imx_ccm->chsccdr);
481
482 /* Enable enet system clock */
483 reg = readl(&imx_ccm->CCGR3);
484 reg |= MXC_CCM_CCGR3_ENET_MASK;
485 writel(reg, &imx_ccm->CCGR3);
486 #endif
487 return 0;
488 }
489 #endif
490
491 static u32 get_usdhc_clk(u32 port)
492 {
493 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
494 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
495 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
496
497 switch (port) {
498 case 0:
499 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
500 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
501 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
502
503 break;
504 case 1:
505 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
506 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
507 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
508
509 break;
510 case 2:
511 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
512 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
513 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
514
515 break;
516 case 3:
517 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
518 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
519 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
520
521 break;
522 default:
523 break;
524 }
525
526 if (clk_sel)
527 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
528 else
529 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
530
531 return root_freq / (usdhc_podf + 1);
532 }
533
534 u32 imx_get_uartclk(void)
535 {
536 return get_uart_clk();
537 }
538
539 u32 imx_get_fecclk(void)
540 {
541 return mxc_get_clock(MXC_IPG_CLK);
542 }
543
544 static int enable_enet_pll(uint32_t en)
545 {
546 struct mxc_ccm_reg *const imx_ccm
547 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
548 s32 timeout = 100000;
549 u32 reg = 0;
550
551 /* Enable PLLs */
552 reg = readl(&imx_ccm->analog_pll_enet);
553 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
554 writel(reg, &imx_ccm->analog_pll_enet);
555 reg |= BM_ANADIG_PLL_SYS_ENABLE;
556 while (timeout--) {
557 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
558 break;
559 }
560 if (timeout <= 0)
561 return -EIO;
562 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
563 writel(reg, &imx_ccm->analog_pll_enet);
564 reg |= en;
565 writel(reg, &imx_ccm->analog_pll_enet);
566 return 0;
567 }
568
569 #ifndef CONFIG_MX6SX
570 static void ungate_sata_clock(void)
571 {
572 struct mxc_ccm_reg *const imx_ccm =
573 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
574
575 /* Enable SATA clock. */
576 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
577 }
578 #endif
579
580 static void ungate_pcie_clock(void)
581 {
582 struct mxc_ccm_reg *const imx_ccm =
583 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
584
585 /* Enable PCIe clock. */
586 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
587 }
588
589 #ifndef CONFIG_MX6SX
590 int enable_sata_clock(void)
591 {
592 ungate_sata_clock();
593 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
594 }
595 #endif
596
597 int enable_pcie_clock(void)
598 {
599 struct anatop_regs *anatop_regs =
600 (struct anatop_regs *)ANATOP_BASE_ADDR;
601 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
602 u32 lvds1_clk_sel;
603
604 /*
605 * Here be dragons!
606 *
607 * The register ANATOP_MISC1 is not documented in the Freescale
608 * MX6RM. The register that is mapped in the ANATOP space and
609 * marked as ANATOP_MISC1 is actually documented in the PMU section
610 * of the datasheet as PMU_MISC1.
611 *
612 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
613 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
614 * for PCI express link that is clocked from the i.MX6.
615 */
616 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
617 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
618 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
619 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
620 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
621
622 if (is_cpu_type(MXC_CPU_MX6SX))
623 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
624 else
625 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
626
627 clrsetbits_le32(&anatop_regs->ana_misc1,
628 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
629 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
630 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
631
632 /* PCIe reference clock sourced from AXI. */
633 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
634
635 /* Party time! Ungate the clock to the PCIe. */
636 #ifndef CONFIG_MX6SX
637 ungate_sata_clock();
638 #endif
639 ungate_pcie_clock();
640
641 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
642 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
643 }
644
645 unsigned int mxc_get_clock(enum mxc_clock clk)
646 {
647 switch (clk) {
648 case MXC_ARM_CLK:
649 return get_mcu_main_clk();
650 case MXC_PER_CLK:
651 return get_periph_clk();
652 case MXC_AHB_CLK:
653 return get_ahb_clk();
654 case MXC_IPG_CLK:
655 return get_ipg_clk();
656 case MXC_IPG_PERCLK:
657 case MXC_I2C_CLK:
658 return get_ipg_per_clk();
659 case MXC_UART_CLK:
660 return get_uart_clk();
661 case MXC_CSPI_CLK:
662 return get_cspi_clk();
663 case MXC_AXI_CLK:
664 return get_axi_clk();
665 case MXC_EMI_SLOW_CLK:
666 return get_emi_slow_clk();
667 case MXC_DDR_CLK:
668 return get_mmdc_ch0_clk();
669 case MXC_ESDHC_CLK:
670 return get_usdhc_clk(0);
671 case MXC_ESDHC2_CLK:
672 return get_usdhc_clk(1);
673 case MXC_ESDHC3_CLK:
674 return get_usdhc_clk(2);
675 case MXC_ESDHC4_CLK:
676 return get_usdhc_clk(3);
677 case MXC_SATA_CLK:
678 return get_ahb_clk();
679 default:
680 break;
681 }
682
683 return -1;
684 }
685
686 /*
687 * Dump some core clockes.
688 */
689 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
690 {
691 u32 freq;
692 freq = decode_pll(PLL_SYS, MXC_HCLK);
693 printf("PLL_SYS %8d MHz\n", freq / 1000000);
694 freq = decode_pll(PLL_BUS, MXC_HCLK);
695 printf("PLL_BUS %8d MHz\n", freq / 1000000);
696 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
697 printf("PLL_OTG %8d MHz\n", freq / 1000000);
698 freq = decode_pll(PLL_ENET, MXC_HCLK);
699 printf("PLL_NET %8d MHz\n", freq / 1000000);
700
701 printf("\n");
702 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
703 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
704 #ifdef CONFIG_MXC_SPI
705 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
706 #endif
707 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
708 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
709 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
710 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
711 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
712 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
713 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
714 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
715 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
716
717 return 0;
718 }
719
720 #ifndef CONFIG_MX6SX
721 void enable_ipu_clock(void)
722 {
723 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
724 int reg;
725 reg = readl(&mxc_ccm->CCGR3);
726 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
727 writel(reg, &mxc_ccm->CCGR3);
728 }
729 #endif
730 /***************************************************/
731
732 U_BOOT_CMD(
733 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
734 "display clocks",
735 ""
736 );
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