arch/arm/cpu/armv7/mx6/ddr.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <linux/types.h>
  10 #include <asm/arch/mx6-ddr.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <asm/types.h>
  14
  15 #if defined(CONFIG_MX6SX)
  16 /* Configure MX6SX mmdc iomux */
  17 void mx6sx_dram_iocfg(unsigned width,
  18                       const struct mx6sx_iomux_ddr_regs *ddr,
  19                       const struct mx6sx_iomux_grp_regs *grp)
  20 {
  21         struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  22         struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  23
  24         mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  25         mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  26
  27         /* DDR IO TYPE */
  28         writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  29         writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  30
  31         /* CLOCK */
  32         writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  33
  34         /* ADDRESS */
  35         writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  36         writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  37         writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  38
  39         /* Control */
  40         writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  41         writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  42         writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  43         writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  44         writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  45         writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  46         writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  47
  48         /* Data Strobes */
  49         writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  50         writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  51         writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  52         if (width >= 32) {
  53                 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  54                 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  55         }
  56
  57         /* Data */
  58         writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  59         writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  60         writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  61         if (width >= 32) {
  62                 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  63                 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  64         }
  65         writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  66         writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  67         if (width >= 32) {
  68                 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  69                 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  70         }
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_MX6UL
  75 void mx6ul_dram_iocfg(unsigned width,
  76                       const struct mx6ul_iomux_ddr_regs *ddr,
  77                       const struct mx6ul_iomux_grp_regs *grp)
  78 {
  79         struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
  80         struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
  81
  82         mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  83         mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
  84
  85         /* DDR IO TYPE */
  86         writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  87         writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  88
  89         /* CLOCK */
  90         writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  91
  92         /* ADDRESS */
  93         writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  94         writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  95         writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  96
  97         /* Control */
  98         writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  99         writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
 100         writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
 101         writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
 102         writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
 103
 104         /* Data Strobes */
 105         writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
 106         writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
 107         writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
 108
 109         /* Data */
 110         writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
 111         writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
 112         writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
 113         writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
 114         writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
 115 }
 116 #endif
 117
 118 #if defined(CONFIG_MX6SL)
 119 void mx6sl_dram_iocfg(unsigned width,
 120                       const struct mx6sl_iomux_ddr_regs *ddr,
 121                       const struct mx6sl_iomux_grp_regs *grp)
 122 {
 123         struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
 124         struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
 125
 126         mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
 127         mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
 128
 129         /* DDR IO TYPE */
 130         mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
 131         mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
 132
 133         /* CLOCK */
 134         mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
 135
 136         /* ADDRESS */
 137         mx6_ddr_iomux->dram_cas = ddr->dram_cas;
 138         mx6_ddr_iomux->dram_ras = ddr->dram_ras;
 139         mx6_grp_iomux->grp_addds = grp->grp_addds;
 140
 141         /* Control */
 142         mx6_ddr_iomux->dram_reset = ddr->dram_reset;
 143         mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
 144         mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
 145
 146         /* Data Strobes */
 147         mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
 148         mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
 149         mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
 150         if (width >= 32) {
 151                 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
 152                 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
 153         }
 154
 155         /* Data */
 156         mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
 157         mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
 158         mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
 159         if (width >= 32) {
 160                 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
 161                 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
 162         }
 163
 164         mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
 165         mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
 166         if (width >= 32) {
 167                 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
 168                 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
 169         }
 170 }
 171 #endif
 172
 173 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 174 /* Configure MX6DQ mmdc iomux */
 175 void mx6dq_dram_iocfg(unsigned width,
 176                       const struct mx6dq_iomux_ddr_regs *ddr,
 177                       const struct mx6dq_iomux_grp_regs *grp)
 178 {
 179         volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
 180         volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
 181
 182         mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
 183         mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
 184
 185         /* DDR IO Type */
 186         mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
 187         mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
 188
 189         /* Clock */
 190         mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
 191         mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
 192
 193         /* Address */
 194         mx6_ddr_iomux->dram_cas = ddr->dram_cas;
 195         mx6_ddr_iomux->dram_ras = ddr->dram_ras;
 196         mx6_grp_iomux->grp_addds = grp->grp_addds;
 197
 198         /* Control */
 199         mx6_ddr_iomux->dram_reset = ddr->dram_reset;
 200         mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
 201         mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
 202         mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
 203         mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
 204         mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
 205         mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
 206
 207         /* Data Strobes */
 208         mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
 209         mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
 210         mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
 211         if (width >= 32) {
 212                 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
 213                 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
 214         }
 215         if (width >= 64) {
 216                 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
 217                 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
 218                 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
 219                 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
 220         }
 221
 222         /* Data */
 223         mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
 224         mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
 225         mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
 226         if (width >= 32) {
 227                 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
 228                 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
 229         }
 230         if (width >= 64) {
 231                 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
 232                 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
 233                 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
 234                 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
 235         }
 236         mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
 237         mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
 238         if (width >= 32) {
 239                 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
 240                 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
 241         }
 242         if (width >= 64) {
 243                 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
 244                 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
 245                 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
 246                 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
 247         }
 248 }
 249 #endif
 250
 251 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 252 /* Configure MX6SDL mmdc iomux */
 253 void mx6sdl_dram_iocfg(unsigned width,
 254                        const struct mx6sdl_iomux_ddr_regs *ddr,
 255                        const struct mx6sdl_iomux_grp_regs *grp)
 256 {
 257         volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
 258         volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
 259
 260         mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
 261         mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
 262
 263         /* DDR IO Type */
 264         mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
 265         mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
 266
 267         /* Clock */
 268         mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
 269         mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
 270
 271         /* Address */
 272         mx6_ddr_iomux->dram_cas = ddr->dram_cas;
 273         mx6_ddr_iomux->dram_ras = ddr->dram_ras;
 274         mx6_grp_iomux->grp_addds = grp->grp_addds;
 275
 276         /* Control */
 277         mx6_ddr_iomux->dram_reset = ddr->dram_reset;
 278         mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
 279         mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
 280         mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
 281         mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
 282         mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
 283         mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
 284
 285         /* Data Strobes */
 286         mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
 287         mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
 288         mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
 289         if (width >= 32) {
 290                 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
 291                 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
 292         }
 293         if (width >= 64) {
 294                 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
 295                 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
 296                 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
 297                 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
 298         }
 299
 300         /* Data */
 301         mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
 302         mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
 303         mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
 304         if (width >= 32) {
 305                 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
 306                 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
 307         }
 308         if (width >= 64) {
 309                 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
 310                 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
 311                 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
 312                 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
 313         }
 314         mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
 315         mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
 316         if (width >= 32) {
 317                 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
 318                 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
 319         }
 320         if (width >= 64) {
 321                 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
 322                 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
 323                 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
 324                 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
 325         }
 326 }
 327 #endif
 328
 329 /*
 330  * Configure mx6 mmdc registers based on:
 331  *  - board-specific memory configuration
 332  *  - board-specific calibration data
 333  *  - ddr3 chip details
 334  *
 335  * The various calculations here are derived from the Freescale
 336  * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
 337  * configuration registers based on memory system and memory chip parameters.
 338  *
 339  * The defaults here are those which were specified in the spreadsheet.
 340  * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
 341  * section titled MMDC initialization
 342  */
 343 #define MR(val, ba, cmd, cs1) \
 344         ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 345 #define MMDC1(entry, value) do {                                          \
 346         if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
 347             !is_cpu_type(MXC_CPU_MX6SL))                                  \
 348                 mmdc1->entry = value;                                     \
 349         } while (0)
 350
 351 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 352                   const struct mx6_mmdc_calibration *calib,
 353                   const struct mx6_ddr3_cfg *ddr3_cfg)
 354 {
 355         volatile struct mmdc_p_regs *mmdc0;
 356         volatile struct mmdc_p_regs *mmdc1;
 357         u32 val;
 358         u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 359         u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 360         u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 361         u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
 362         u16 cs0_end;
 363         u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 364         u8 coladdr;
 365         int clkper; /* clock period in picoseconds */
 366         int clock; /* clock freq in MHz */
 367         int cs;
 368         u16 mem_speed = ddr3_cfg->mem_speed;
 369
 370         mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 371         if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
 372             !is_cpu_type(MXC_CPU_MX6SL))
 373                 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 374
 375         /* Limit mem_speed for MX6D/MX6Q */
 376         if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
 377                 if (mem_speed > 1066)
 378                         mem_speed = 1066; /* 1066 MT/s */
 379
 380                 tcwl = 4;
 381         }
 382         /* Limit mem_speed for MX6S/MX6DL */
 383         else {
 384                 if (mem_speed > 800)
 385                         mem_speed = 800;  /* 800 MT/s */
 386
 387                 tcwl = 3;
 388         }
 389
 390         clock = mem_speed / 2;
 391         /*
 392          * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 393          * up to 528 MHz, so reduce the clock to fit chip specs
 394          */
 395         if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
 396                 if (clock > 528)
 397                         clock = 528; /* 528 MHz */
 398         }
 399
 400         clkper = (1000 * 1000) / clock; /* pico seconds */
 401         todtlon = tcwl;
 402         taxpd = tcwl;
 403         tanpd = tcwl;
 404
 405         switch (ddr3_cfg->density) {
 406         case 1: /* 1Gb per chip */
 407                 trfc = DIV_ROUND_UP(110000, clkper) - 1;
 408                 txs = DIV_ROUND_UP(120000, clkper) - 1;
 409                 break;
 410         case 2: /* 2Gb per chip */
 411                 trfc = DIV_ROUND_UP(160000, clkper) - 1;
 412                 txs = DIV_ROUND_UP(170000, clkper) - 1;
 413                 break;
 414         case 4: /* 4Gb per chip */
 415                 trfc = DIV_ROUND_UP(300000, clkper) - 1;
 416                 txs = DIV_ROUND_UP(310000, clkper) - 1;
 417                 break;
 418         case 8: /* 8Gb per chip */
 419                 trfc = DIV_ROUND_UP(350000, clkper) - 1;
 420                 txs = DIV_ROUND_UP(360000, clkper) - 1;
 421                 break;
 422         default:
 423                 /* invalid density */
 424                 puts("invalid chip density\n");
 425                 hang();
 426                 break;
 427         }
 428         txpr = txs;
 429
 430         switch (mem_speed) {
 431         case 800:
 432                 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
 433                 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
 434                 if (ddr3_cfg->pagesz == 1) {
 435                         tfaw = DIV_ROUND_UP(40000, clkper) - 1;
 436                         trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 437                 } else {
 438                         tfaw = DIV_ROUND_UP(50000, clkper) - 1;
 439                         trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 440                 }
 441                 break;
 442         case 1066:
 443                 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
 444                 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
 445                 if (ddr3_cfg->pagesz == 1) {
 446                         tfaw = DIV_ROUND_UP(37500, clkper) - 1;
 447                         trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
 448                 } else {
 449                         tfaw = DIV_ROUND_UP(50000, clkper) - 1;
 450                         trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 451                 }
 452                 break;
 453         default:
 454                 puts("invalid memory speed\n");
 455                 hang();
 456                 break;
 457         }
 458         txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
 459         tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
 460         taonpd = DIV_ROUND_UP(2000, clkper) - 1;
 461         tcksrx = tcksre;
 462         taofpd = taonpd;
 463         twr  = DIV_ROUND_UP(15000, clkper) - 1;
 464         tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
 465         trc  = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
 466         tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
 467         tcl  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
 468         trp  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
 469         twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
 470         trcd = trp;
 471         trtp = twtr;
 472         cs0_end = 4 * sysinfo->cs_density - 1;
 473
 474         debug("density:%d Gb (%d Gb per chip)\n",
 475               sysinfo->cs_density, ddr3_cfg->density);
 476         debug("clock: %dMHz (%d ps)\n", clock, clkper);
 477         debug("memspd:%d\n", mem_speed);
 478         debug("tcke=%d\n", tcke);
 479         debug("tcksrx=%d\n", tcksrx);
 480         debug("tcksre=%d\n", tcksre);
 481         debug("taofpd=%d\n", taofpd);
 482         debug("taonpd=%d\n", taonpd);
 483         debug("todtlon=%d\n", todtlon);
 484         debug("tanpd=%d\n", tanpd);
 485         debug("taxpd=%d\n", taxpd);
 486         debug("trfc=%d\n", trfc);
 487         debug("txs=%d\n", txs);
 488         debug("txp=%d\n", txp);
 489         debug("txpdll=%d\n", txpdll);
 490         debug("tfaw=%d\n", tfaw);
 491         debug("tcl=%d\n", tcl);
 492         debug("trcd=%d\n", trcd);
 493         debug("trp=%d\n", trp);
 494         debug("trc=%d\n", trc);
 495         debug("tras=%d\n", tras);
 496         debug("twr=%d\n", twr);
 497         debug("tmrd=%d\n", tmrd);
 498         debug("tcwl=%d\n", tcwl);
 499         debug("tdllk=%d\n", tdllk);
 500         debug("trtp=%d\n", trtp);
 501         debug("twtr=%d\n", twtr);
 502         debug("trrd=%d\n", trrd);
 503         debug("txpr=%d\n", txpr);
 504         debug("cs0_end=%d\n", cs0_end);
 505         debug("ncs=%d\n", sysinfo->ncs);
 506         debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
 507         debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
 508         debug("SRT=%d\n", ddr3_cfg->SRT);
 509         debug("tcl=%d\n", tcl);
 510         debug("twr=%d\n", twr);
 511
 512         /*
 513          * board-specific configuration:
 514          *  These values are determined empirically and vary per board layout
 515          *  see:
 516          *   appnote, ddr3 spreadsheet
 517          */
 518         mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
 519         mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
 520         mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
 521         mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
 522         mmdc0->mprddlctl = calib->p0_mprddlctl;
 523         mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
 524         if (sysinfo->dsize > 1) {
 525                 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
 526                 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
 527                 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
 528                 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
 529                 MMDC1(mprddlctl, calib->p1_mprddlctl);
 530                 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
 531         }
 532
 533         /* Read data DQ Byte0-3 delay */
 534         mmdc0->mprddqby0dl = 0x33333333;
 535         mmdc0->mprddqby1dl = 0x33333333;
 536         if (sysinfo->dsize > 0) {
 537                 mmdc0->mprddqby2dl = 0x33333333;
 538                 mmdc0->mprddqby3dl = 0x33333333;
 539         }
 540
 541         if (sysinfo->dsize > 1) {
 542                 MMDC1(mprddqby0dl, 0x33333333);
 543                 MMDC1(mprddqby1dl, 0x33333333);
 544                 MMDC1(mprddqby2dl, 0x33333333);
 545                 MMDC1(mprddqby3dl, 0x33333333);
 546         }
 547
 548         /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
 549         val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
 550         mmdc0->mpodtctrl = val;
 551         if (sysinfo->dsize > 1)
 552                 MMDC1(mpodtctrl, val);
 553
 554         /* complete calibration */
 555         val = (1 << 11); /* Force measurement on delay-lines */
 556         mmdc0->mpmur0 = val;
 557         if (sysinfo->dsize > 1)
 558                 MMDC1(mpmur0, val);
 559
 560         /* Step 1: configuration request */
 561         mmdc0->mdscr = (u32)(1 << 15); /* config request */
 562
 563         /* Step 2: Timing configuration */
 564         mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
 565                         (txpdll << 9) | (tfaw << 4) | tcl;
 566         mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
 567                         (tras << 16) | (1 << 15) /* trpa */ |
 568                         (twr << 9) | (tmrd << 5) | tcwl;
 569         mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
 570         mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
 571                        (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
 572         mmdc0->mdasp = cs0_end; /* CS addressing */
 573
 574         /* Step 3: Configure DDR type */
 575         mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
 576                         (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
 577                         (sysinfo->ralat << 6);
 578
 579         /* Step 4: Configure delay while leaving reset */
 580         mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
 581                       (sysinfo->rst_to_cke << 0);
 582
 583         /* Step 5: Configure DDR physical parameters (density and burst len) */
 584         coladdr = ddr3_cfg->coladdr;
 585         if (ddr3_cfg->coladdr == 8)             /* 8-bit COL is 0x3 */
 586                 coladdr += 4;
 587         else if (ddr3_cfg->coladdr == 12)       /* 12-bit COL is 0x4 */
 588                 coladdr += 1;
 589         mmdc0->mdctl =  (ddr3_cfg->rowaddr - 11) << 24 |        /* ROW */
 590                         (coladdr - 9) << 20 |                   /* COL */
 591                         (1 << 19) |             /* Burst Length = 8 for DDR3 */
 592                         (sysinfo->dsize << 16);         /* DDR data bus size */
 593
 594         /* Step 6: Perform ZQ calibration */
 595         val = 0xa1390001; /* one-time HW ZQ calib */
 596         mmdc0->mpzqhwctrl = val;
 597         if (sysinfo->dsize > 1)
 598                 MMDC1(mpzqhwctrl, val);
 599
 600         /* Step 7: Enable MMDC with desired chip select */
 601         mmdc0->mdctl |= (1 << 31) |                          /* SDE_0 for CS0 */
 602                         ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
 603
 604         /* Step 8: Write Mode Registers to Init DDR3 devices */
 605         for (cs = 0; cs < sysinfo->ncs; cs++) {
 606                 /* MR2 */
 607                 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
 608                       ((tcwl - 3) & 3) << 3;
 609                 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
 610                 mmdc0->mdscr = MR(val, 2, 3, cs);
 611                 /* MR3 */
 612                 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
 613                 mmdc0->mdscr = MR(0, 3, 3, cs);
 614                 /* MR1 */
 615                 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
 616                       ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
 617                 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
 618                 mmdc0->mdscr = MR(val, 1, 3, cs);
 619                 /* MR0 */
 620                 val = ((tcl - 1) << 4) |        /* CAS */
 621                       (1 << 8)   |              /* DLL Reset */
 622                       ((twr - 3) << 9) |        /* Write Recovery */
 623                       (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
 624                 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
 625                 mmdc0->mdscr = MR(val, 0, 3, cs);
 626                 /* ZQ calibration */
 627                 val = (1 << 10);
 628                 mmdc0->mdscr = MR(val, 0, 4, cs);
 629         }
 630
 631         /* Step 10: Power down control and self-refresh */
 632         mmdc0->mdpdc = (tcke & 0x7) << 16 |
 633                         5            << 12 |  /* PWDT_1: 256 cycles */
 634                         5            <<  8 |  /* PWDT_0: 256 cycles */
 635                         1            <<  6 |  /* BOTH_CS_PD */
 636                         (tcksrx & 0x7) << 3 |
 637                         (tcksre & 0x7);
 638         if (!sysinfo->pd_fast_exit)
 639                 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
 640         mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
 641
 642         /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
 643         val = 0xa1390003;
 644         mmdc0->mpzqhwctrl = val;
 645         if (sysinfo->dsize > 1)
 646                 MMDC1(mpzqhwctrl, val);
 647
 648         /* Step 12: Configure and activate periodic refresh */
 649         mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
 650                        (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
 651
 652         /* Step 13: Deassert config request - init complete */
 653         mmdc0->mdscr = 0x00000000;
 654
 655         /* wait for auto-ZQ calibration to complete */
 656         mdelay(1);
 657 }
 658
 659 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 660                   const struct mx6_mmdc_calibration *calib,
 661                   const void *ddr_cfg)
 662 {
 663         if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
 664                 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
 665         } else {
 666                 puts("Unsupported ddr type\n");
 667                 hang();
 668         }
 669 }