arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/dma.h>
  18 #include <stdbool.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/crm_regs.h>
  21
  22 enum ldo_reg {
  23         LDO_ARM,
  24         LDO_SOC,
  25         LDO_PU,
  26 };
  27
  28 struct scu_regs {
  29         u32     ctrl;
  30         u32     config;
  31         u32     status;
  32         u32     invalidate;
  33         u32     fpga_rev;
  34 };
  35
  36 u32 get_cpu_rev(void)
  37 {
  38         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  39         u32 reg = readl(&anatop->digprog_sololite);
  40         u32 type = ((reg >> 16) & 0xff);
  41
  42         if (type != MXC_CPU_MX6SL) {
  43                 reg = readl(&anatop->digprog);
  44                 type = ((reg >> 16) & 0xff);
  45                 if (type == MXC_CPU_MX6DL) {
  46                         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  47                         u32 cfg = readl(&scu->config) & 3;
  48
  49                         if (!cfg)
  50                                 type = MXC_CPU_MX6SOLO;
  51                 }
  52         }
  53         reg &= 0xff;            /* mx6 silicon revision */
  54         return (type << 12) | (reg + 0x10);
  55 }
  56
  57 #ifdef CONFIG_REVISION_TAG
  58 u32 __weak get_board_rev(void)
  59 {
  60         u32 cpurev = get_cpu_rev();
  61         u32 type = ((cpurev >> 12) & 0xff);
  62         if (type == MXC_CPU_MX6SOLO)
  63                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  64
  65         return cpurev;
  66 }
  67 #endif
  68
  69 void init_aips(void)
  70 {
  71         struct aipstz_regs *aips1, *aips2;
  72
  73         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  74         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  75
  76         /*
  77          * Set all MPROTx to be non-bufferable, trusted for R/W,
  78          * not forced to user-mode.
  79          */
  80         writel(0x77777777, &aips1->mprot0);
  81         writel(0x77777777, &aips1->mprot1);
  82         writel(0x77777777, &aips2->mprot0);
  83         writel(0x77777777, &aips2->mprot1);
  84
  85         /*
  86          * Set all OPACRx to be non-bufferable, not require
  87          * supervisor privilege level for access,allow for
  88          * write access and untrusted master access.
  89          */
  90         writel(0x00000000, &aips1->opacr0);
  91         writel(0x00000000, &aips1->opacr1);
  92         writel(0x00000000, &aips1->opacr2);
  93         writel(0x00000000, &aips1->opacr3);
  94         writel(0x00000000, &aips1->opacr4);
  95         writel(0x00000000, &aips2->opacr0);
  96         writel(0x00000000, &aips2->opacr1);
  97         writel(0x00000000, &aips2->opacr2);
  98         writel(0x00000000, &aips2->opacr3);
  99         writel(0x00000000, &aips2->opacr4);
 100 }
 101
 102 static void clear_ldo_ramp(void)
 103 {
 104         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 105         int reg;
 106
 107         /* ROM may modify LDO ramp up time according to fuse setting, so in
 108          * order to be in the safe side we neeed to reset these settings to
 109          * match the reset value: 0'b00
 110          */
 111         reg = readl(&anatop->ana_misc2);
 112         reg &= ~(0x3f << 24);
 113         writel(reg, &anatop->ana_misc2);
 114 }
 115
 116 /*
 117  * Set the VDDSOC
 118  *
 119  * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 120  * them to the specified millivolt level.
 121  * Possible values are from 0.725V to 1.450V in steps of
 122  * 0.025V (25mV).
 123  */
 124 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 125 {
 126         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 127         u32 val, step, old, reg = readl(&anatop->reg_core);
 128         u8 shift;
 129
 130         if (mv < 725)
 131                 val = 0x00;     /* Power gated off */
 132         else if (mv > 1450)
 133                 val = 0x1F;     /* Power FET switched full on. No regulation */
 134         else
 135                 val = (mv - 700) / 25;
 136
 137         clear_ldo_ramp();
 138
 139         switch (ldo) {
 140         case LDO_SOC:
 141                 shift = 18;
 142                 break;
 143         case LDO_PU:
 144                 shift = 9;
 145                 break;
 146         case LDO_ARM:
 147                 shift = 0;
 148                 break;
 149         default:
 150                 return -EINVAL;
 151         }
 152
 153         old = (reg & (0x1F << shift)) >> shift;
 154         step = abs(val - old);
 155         if (step == 0)
 156                 return 0;
 157
 158         reg = (reg & ~(0x1F << shift)) | (val << shift);
 159         writel(reg, &anatop->reg_core);
 160
 161         /*
 162          * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 163          * step
 164          */
 165         udelay(3 * step);
 166
 167         return 0;
 168 }
 169
 170 static void imx_set_wdog_powerdown(bool enable)
 171 {
 172         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 173         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 174
 175         /* Write to the PDE (Power Down Enable) bit */
 176         writew(enable, &wdog1->wmcr);
 177         writew(enable, &wdog2->wmcr);
 178 }
 179
 180 int arch_cpu_init(void)
 181 {
 182         init_aips();
 183
 184         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 185
 186 #ifdef CONFIG_APBH_DMA
 187         /* Start APBH DMA */
 188         mxs_dma_init();
 189 #endif
 190
 191         return 0;
 192 }
 193
 194 int board_postclk_init(void)
 195 {
 196         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 197
 198         return 0;
 199 }
 200
 201 #ifndef CONFIG_SYS_DCACHE_OFF
 202 void enable_caches(void)
 203 {
 204         /* Avoid random hang when download by usb */
 205         invalidate_dcache_all();
 206         /* Enable D-cache. I-cache is already enabled in start.S */
 207         dcache_enable();
 208 }
 209 #endif
 210
 211 #if defined(CONFIG_FEC_MXC)
 212 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 213 {
 214         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 215         struct fuse_bank *bank = &ocotp->bank[4];
 216         struct fuse_bank4_regs *fuse =
 217                         (struct fuse_bank4_regs *)bank->fuse_regs;
 218
 219         u32 value = readl(&fuse->mac_addr_high);
 220         mac[0] = (value >> 8);
 221         mac[1] = value ;
 222
 223         value = readl(&fuse->mac_addr_low);
 224         mac[2] = value >> 24 ;
 225         mac[3] = value >> 16 ;
 226         mac[4] = value >> 8 ;
 227         mac[5] = value ;
 228
 229 }
 230 #endif
 231
 232 void boot_mode_apply(unsigned cfg_val)
 233 {
 234         unsigned reg;
 235         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 236         writel(cfg_val, &psrc->gpr9);
 237         reg = readl(&psrc->gpr10);
 238         if (cfg_val)
 239                 reg |= 1 << 28;
 240         else
 241                 reg &= ~(1 << 28);
 242         writel(reg, &psrc->gpr10);
 243 }
 244 /*
 245  * cfg_val will be used for
 246  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 247  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 248  * to SBMR1, which will determine the boot device.
 249  */
 250 const struct boot_mode soc_boot_modes[] = {
 251         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 252         /* reserved value should start rom usb */
 253         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 254         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 255         {"escpi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 256         {"escpi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 257         {"escpi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 258         {"escpi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 259         /* 4 bit bus width */
 260         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 261         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 262         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 263         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 264         {NULL,          0},
 265 };
 266
 267 void s_init(void)
 268 {
 269         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 270         int is_6q = is_cpu_type(MXC_CPU_MX6Q);
 271         u32 mask480;
 272         u32 mask528;
 273
 274         /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 275          * to make sure PFD is working right, otherwise, PFDs may
 276          * not output clock after reset, MX6DL and MX6SL have added 396M pfd
 277          * workaround in ROM code, as bus clock need it
 278          */
 279
 280         mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
 281                 ANATOP_PFD_CLKGATE_MASK(1) |
 282                 ANATOP_PFD_CLKGATE_MASK(2) |
 283                 ANATOP_PFD_CLKGATE_MASK(3);
 284         mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
 285                 ANATOP_PFD_CLKGATE_MASK(1) |
 286                 ANATOP_PFD_CLKGATE_MASK(3);
 287
 288         /*
 289          * Don't reset PFD2 on DL/S
 290          */
 291         if (is_6q)
 292                 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 293         writel(mask480, &anatop->pfd_480_set);
 294         writel(mask528, &anatop->pfd_528_set);
 295         writel(mask480, &anatop->pfd_480_clr);
 296         writel(mask528, &anatop->pfd_528_clr);
 297 }
 298
 299 #ifdef CONFIG_IMX_HDMI
 300 void imx_enable_hdmi_phy(void)
 301 {
 302         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 303         u8 reg;
 304         reg = readb(&hdmi->phy_conf0);
 305         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 306         writeb(reg, &hdmi->phy_conf0);
 307         udelay(3000);
 308         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 309         writeb(reg, &hdmi->phy_conf0);
 310         udelay(3000);
 311         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 312         writeb(reg, &hdmi->phy_conf0);
 313         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 314 }
 315
 316 void imx_setup_hdmi(void)
 317 {
 318         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 319         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 320         int reg;
 321
 322         /* Turn on HDMI PHY clock */
 323         reg = readl(&mxc_ccm->CCGR2);
 324         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 325                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 326         writel(reg, &mxc_ccm->CCGR2);
 327         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 328         reg = readl(&mxc_ccm->chsccdr);
 329         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 330                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 331                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 332         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 333                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 334                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 335                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 336         writel(reg, &mxc_ccm->chsccdr);
 337 }
 338 #endif