arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <linux/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/dma.h>
  18 #include <asm/imx-common/hab.h>
  19 #include <stdbool.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <dm.h>
  23 #include <imx_thermal.h>
  24 #include <mmc.h>
  25
  26 enum ldo_reg {
  27         LDO_ARM,
  28         LDO_SOC,
  29         LDO_PU,
  30 };
  31
  32 struct scu_regs {
  33         u32     ctrl;
  34         u32     config;
  35         u32     status;
  36         u32     invalidate;
  37         u32     fpga_rev;
  38 };
  39
  40 #if defined(CONFIG_IMX_THERMAL)
  41 static const struct imx_thermal_plat imx6_thermal_plat = {
  42         .regs = (void *)ANATOP_BASE_ADDR,
  43         .fuse_bank = 1,
  44         .fuse_word = 6,
  45 };
  46
  47 U_BOOT_DEVICE(imx6_thermal) = {
  48         .name = "imx_thermal",
  49         .platdata = &imx6_thermal_plat,
  50 };
  51 #endif
  52
  53 #if defined(CONFIG_SECURE_BOOT)
  54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  55         .bank = 0,
  56         .word = 6,
  57 };
  58 #endif
  59
  60 u32 get_nr_cpus(void)
  61 {
  62         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  63         return readl(&scu->config) & 3;
  64 }
  65
  66 u32 get_cpu_rev(void)
  67 {
  68         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  69         u32 reg = readl(&anatop->digprog_sololite);
  70         u32 type = ((reg >> 16) & 0xff);
  71         u32 major, cfg = 0;
  72
  73         if (type != MXC_CPU_MX6SL) {
  74                 reg = readl(&anatop->digprog);
  75                 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  76                 cfg = readl(&scu->config) & 3;
  77                 type = ((reg >> 16) & 0xff);
  78                 if (type == MXC_CPU_MX6DL) {
  79                         if (!cfg)
  80                                 type = MXC_CPU_MX6SOLO;
  81                 }
  82
  83                 if (type == MXC_CPU_MX6Q) {
  84                         if (cfg == 1)
  85                                 type = MXC_CPU_MX6D;
  86                 }
  87
  88         }
  89         major = ((reg >> 8) & 0xff);
  90         if ((major >= 1) &&
  91             ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  92                 major--;
  93                 type = MXC_CPU_MX6QP;
  94                 if (cfg == 1)
  95                         type = MXC_CPU_MX6DP;
  96         }
  97         reg &= 0xff;            /* mx6 silicon revision */
  98         return (type << 12) | (reg + (0x10 * (major + 1)));
  99 }
 100
 101 /*
 102  * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
 103  * defines a 2-bit SPEED_GRADING
 104  */
 105 #define OCOTP_CFG3_SPEED_SHIFT  16
 106 #define OCOTP_CFG3_SPEED_800MHZ 0
 107 #define OCOTP_CFG3_SPEED_850MHZ 1
 108 #define OCOTP_CFG3_SPEED_1GHZ   2
 109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
 110
 111 /*
 112  * For i.MX6UL
 113  */
 114 #define OCOTP_CFG3_SPEED_528MHZ 1
 115 #define OCOTP_CFG3_SPEED_696MHZ 2
 116
 117 u32 get_cpu_speed_grade_hz(void)
 118 {
 119         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 120         struct fuse_bank *bank = &ocotp->bank[0];
 121         struct fuse_bank0_regs *fuse =
 122                 (struct fuse_bank0_regs *)bank->fuse_regs;
 123         uint32_t val;
 124
 125         val = readl(&fuse->cfg3);
 126         val >>= OCOTP_CFG3_SPEED_SHIFT;
 127         val &= 0x3;
 128
 129         if (is_mx6ul() || is_mx6ull()) {
 130                 if (val == OCOTP_CFG3_SPEED_528MHZ)
 131                         return 528000000;
 132                 else if (val == OCOTP_CFG3_SPEED_696MHZ)
 133                         return 69600000;
 134                 else
 135                         return 0;
 136         }
 137
 138         switch (val) {
 139         /* Valid for IMX6DQ */
 140         case OCOTP_CFG3_SPEED_1P2GHZ:
 141                 if (is_mx6dq() || is_mx6dqp())
 142                         return 1200000000;
 143         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 144         case OCOTP_CFG3_SPEED_1GHZ:
 145                 return 996000000;
 146         /* Valid for IMX6DQ */
 147         case OCOTP_CFG3_SPEED_850MHZ:
 148                 if (is_mx6dq() || is_mx6dqp())
 149                         return 852000000;
 150         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 151         case OCOTP_CFG3_SPEED_800MHZ:
 152                 return 792000000;
 153         }
 154         return 0;
 155 }
 156
 157 /*
 158  * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
 159  * defines a 2-bit Temperature Grade
 160  *
 161  * return temperature grade and min/max temperature in celcius
 162  */
 163 #define OCOTP_MEM0_TEMP_SHIFT          6
 164
 165 u32 get_cpu_temp_grade(int *minc, int *maxc)
 166 {
 167         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 168         struct fuse_bank *bank = &ocotp->bank[1];
 169         struct fuse_bank1_regs *fuse =
 170                 (struct fuse_bank1_regs *)bank->fuse_regs;
 171         uint32_t val;
 172
 173         val = readl(&fuse->mem0);
 174         val >>= OCOTP_MEM0_TEMP_SHIFT;
 175         val &= 0x3;
 176
 177         if (minc && maxc) {
 178                 if (val == TEMP_AUTOMOTIVE) {
 179                         *minc = -40;
 180                         *maxc = 125;
 181                 } else if (val == TEMP_INDUSTRIAL) {
 182                         *minc = -40;
 183                         *maxc = 105;
 184                 } else if (val == TEMP_EXTCOMMERCIAL) {
 185                         *minc = -20;
 186                         *maxc = 105;
 187                 } else {
 188                         *minc = 0;
 189                         *maxc = 95;
 190                 }
 191         }
 192         return val;
 193 }
 194
 195 #ifdef CONFIG_REVISION_TAG
 196 u32 __weak get_board_rev(void)
 197 {
 198         u32 cpurev = get_cpu_rev();
 199         u32 type = ((cpurev >> 12) & 0xff);
 200         if (type == MXC_CPU_MX6SOLO)
 201                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 202
 203         if (type == MXC_CPU_MX6D)
 204                 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
 205
 206         return cpurev;
 207 }
 208 #endif
 209
 210 static void clear_ldo_ramp(void)
 211 {
 212         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 213         int reg;
 214
 215         /* ROM may modify LDO ramp up time according to fuse setting, so in
 216          * order to be in the safe side we neeed to reset these settings to
 217          * match the reset value: 0'b00
 218          */
 219         reg = readl(&anatop->ana_misc2);
 220         reg &= ~(0x3f << 24);
 221         writel(reg, &anatop->ana_misc2);
 222 }
 223
 224 /*
 225  * Set the PMU_REG_CORE register
 226  *
 227  * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 228  * Possible values are from 0.725V to 1.450V in steps of
 229  * 0.025V (25mV).
 230  */
 231 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 232 {
 233         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 234         u32 val, step, old, reg = readl(&anatop->reg_core);
 235         u8 shift;
 236
 237         if (mv < 725)
 238                 val = 0x00;     /* Power gated off */
 239         else if (mv > 1450)
 240                 val = 0x1F;     /* Power FET switched full on. No regulation */
 241         else
 242                 val = (mv - 700) / 25;
 243
 244         clear_ldo_ramp();
 245
 246         switch (ldo) {
 247         case LDO_SOC:
 248                 shift = 18;
 249                 break;
 250         case LDO_PU:
 251                 shift = 9;
 252                 break;
 253         case LDO_ARM:
 254                 shift = 0;
 255                 break;
 256         default:
 257                 return -EINVAL;
 258         }
 259
 260         old = (reg & (0x1F << shift)) >> shift;
 261         step = abs(val - old);
 262         if (step == 0)
 263                 return 0;
 264
 265         reg = (reg & ~(0x1F << shift)) | (val << shift);
 266         writel(reg, &anatop->reg_core);
 267
 268         /*
 269          * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 270          * step
 271          */
 272         udelay(3 * step);
 273
 274         return 0;
 275 }
 276
 277 static void set_ahb_rate(u32 val)
 278 {
 279         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 280         u32 reg, div;
 281
 282         div = get_periph_clk() / val - 1;
 283         reg = readl(&mxc_ccm->cbcdr);
 284
 285         writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
 286                 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 287 }
 288
 289 static void clear_mmdc_ch_mask(void)
 290 {
 291         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 292         u32 reg;
 293         reg = readl(&mxc_ccm->ccdr);
 294
 295         /* Clear MMDC channel mask */
 296         if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
 297                 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
 298         else
 299                 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 300         writel(reg, &mxc_ccm->ccdr);
 301 }
 302
 303 static void init_bandgap(void)
 304 {
 305         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 306         /*
 307          * Ensure the bandgap has stabilized.
 308          */
 309         while (!(readl(&anatop->ana_misc0) & 0x80))
 310                 ;
 311         /*
 312          * For best noise performance of the analog blocks using the
 313          * outputs of the bandgap, the reftop_selfbiasoff bit should
 314          * be set.
 315          */
 316         writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
 317         /*
 318          * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
 319          * VBGADJ bits to 2b'110 to adjust it.
 320          */
 321         if (is_mx6ull())
 322                 writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
 323 }
 324
 325
 326 #ifdef CONFIG_MX6SL
 327 static void set_preclk_from_osc(void)
 328 {
 329         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 330         u32 reg;
 331
 332         reg = readl(&mxc_ccm->cscmr1);
 333         reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
 334         writel(reg, &mxc_ccm->cscmr1);
 335 }
 336 #endif
 337
 338 int arch_cpu_init(void)
 339 {
 340         init_aips();
 341
 342         /* Need to clear MMDC_CHx_MASK to make warm reset work. */
 343         clear_mmdc_ch_mask();
 344
 345         /*
 346          * Disable self-bias circuit in the analog bandap.
 347          * The self-bias circuit is used by the bandgap during startup.
 348          * This bit should be set after the bandgap has initialized.
 349          */
 350         init_bandgap();
 351
 352         if (!is_mx6ul() && !is_mx6ull()) {
 353                 /*
 354                  * When low freq boot is enabled, ROM will not set AHB
 355                  * freq, so we need to ensure AHB freq is 132MHz in such
 356                  * scenario.
 357                  *
 358                  * To i.MX6UL, when power up, default ARM core and
 359                  * AHB rate is 396M and 132M.
 360                  */
 361                 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
 362                         set_ahb_rate(132000000);
 363         }
 364
 365         if (is_mx6ul() && is_soc_rev(CHIP_REV_1_0) == 0) {
 366                 /*
 367                  * According to the design team's requirement on i.MX6UL,
 368                  * the PMIC_STBY_REQ PAD should be configured as open
 369                  * drain 100K (0x0000b8a0).
 370                  * Only exists on TO1.0
 371                  */
 372                 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
 373         }
 374
 375         if (is_mx6ull()) {
 376                 /*
 377                  * GPBIT[1:0] is suggested to set to 2'b11:
 378                  * 2'b00 : always PUP100K
 379                  * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
 380                  * 2'b10 : always disable PUP100K
 381                  * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
 382                  * register offset is different from i.MX6UL, since
 383                  * i.MX6UL is fixed by ECO.
 384                  */
 385                 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
 386                         0x3, MX6UL_SNVS_LP_BASE_ADDR);
 387         }
 388
 389         /* Set perclk to source from OSC 24MHz */
 390 #if defined(CONFIG_MX6SL)
 391         set_preclk_from_osc();
 392 #endif
 393
 394         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 395
 396 #ifdef CONFIG_APBH_DMA
 397         /* Start APBH DMA */
 398         mxs_dma_init();
 399 #endif
 400
 401         init_src();
 402
 403         return 0;
 404 }
 405
 406 #ifdef CONFIG_ENV_IS_IN_MMC
 407 __weak int board_mmc_get_env_dev(int devno)
 408 {
 409         return CONFIG_SYS_MMC_ENV_DEV;
 410 }
 411
 412 static int mmc_get_boot_dev(void)
 413 {
 414         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 415         u32 soc_sbmr = readl(&src_regs->sbmr1);
 416         u32 bootsel;
 417         int devno;
 418
 419         /*
 420          * Refer to
 421          * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
 422          * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
 423          * i.MX6SL/SX/UL has same layout.
 424          */
 425         bootsel = (soc_sbmr & 0x000000FF) >> 6;
 426
 427         /* No boot from sd/mmc */
 428         if (bootsel != 1)
 429                 return -1;
 430
 431         /* BOOT_CFG2[3] and BOOT_CFG2[4] */
 432         devno = (soc_sbmr & 0x00001800) >> 11;
 433
 434         return devno;
 435 }
 436
 437 int mmc_get_env_dev(void)
 438 {
 439         int devno = mmc_get_boot_dev();
 440
 441         /* If not boot from sd/mmc, use default value */
 442         if (devno < 0)
 443                 return CONFIG_SYS_MMC_ENV_DEV;
 444
 445         return board_mmc_get_env_dev(devno);
 446 }
 447
 448 #ifdef CONFIG_SYS_MMC_ENV_PART
 449 __weak int board_mmc_get_env_part(int devno)
 450 {
 451         return CONFIG_SYS_MMC_ENV_PART;
 452 }
 453
 454 uint mmc_get_env_part(struct mmc *mmc)
 455 {
 456         int devno = mmc_get_boot_dev();
 457
 458         /* If not boot from sd/mmc, use default value */
 459         if (devno < 0)
 460                 return CONFIG_SYS_MMC_ENV_PART;
 461
 462         return board_mmc_get_env_part(devno);
 463 }
 464 #endif
 465 #endif
 466
 467 int board_postclk_init(void)
 468 {
 469         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 470
 471         return 0;
 472 }
 473
 474 #if defined(CONFIG_FEC_MXC)
 475 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 476 {
 477         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 478         struct fuse_bank *bank = &ocotp->bank[4];
 479         struct fuse_bank4_regs *fuse =
 480                         (struct fuse_bank4_regs *)bank->fuse_regs;
 481
 482         if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
 483                 u32 value = readl(&fuse->mac_addr2);
 484                 mac[0] = value >> 24 ;
 485                 mac[1] = value >> 16 ;
 486                 mac[2] = value >> 8 ;
 487                 mac[3] = value ;
 488
 489                 value = readl(&fuse->mac_addr1);
 490                 mac[4] = value >> 24 ;
 491                 mac[5] = value >> 16 ;
 492
 493         } else {
 494                 u32 value = readl(&fuse->mac_addr1);
 495                 mac[0] = (value >> 8);
 496                 mac[1] = value ;
 497
 498                 value = readl(&fuse->mac_addr0);
 499                 mac[2] = value >> 24 ;
 500                 mac[3] = value >> 16 ;
 501                 mac[4] = value >> 8 ;
 502                 mac[5] = value ;
 503         }
 504
 505 }
 506 #endif
 507
 508 /*
 509  * cfg_val will be used for
 510  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 511  * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 512  * instead of SBMR1 to determine the boot device.
 513  */
 514 const struct boot_mode soc_boot_modes[] = {
 515         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 516         /* reserved value should start rom usb */
 517         {"usb",         MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 518         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 519         {"ecspi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 520         {"ecspi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 521         {"ecspi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 522         {"ecspi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 523         /* 4 bit bus width */
 524         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 525         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 526         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 527         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 528         {NULL,          0},
 529 };
 530
 531 void reset_misc(void)
 532 {
 533 #ifdef CONFIG_VIDEO_MXS
 534         lcdif_power_down();
 535 #endif
 536 }
 537
 538 void s_init(void)
 539 {
 540         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 541         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 542         u32 mask480;
 543         u32 mask528;
 544         u32 reg, periph1, periph2;
 545
 546         if (is_mx6sx() || is_mx6ul() || is_mx6ull())
 547                 return;
 548
 549         /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 550          * to make sure PFD is working right, otherwise, PFDs may
 551          * not output clock after reset, MX6DL and MX6SL have added 396M pfd
 552          * workaround in ROM code, as bus clock need it
 553          */
 554
 555         mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
 556                 ANATOP_PFD_CLKGATE_MASK(1) |
 557                 ANATOP_PFD_CLKGATE_MASK(2) |
 558                 ANATOP_PFD_CLKGATE_MASK(3);
 559         mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
 560                 ANATOP_PFD_CLKGATE_MASK(3);
 561
 562         reg = readl(&ccm->cbcmr);
 563         periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
 564                 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
 565         periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
 566                 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
 567
 568         /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
 569         if ((periph2 != 0x2) && (periph1 != 0x2))
 570                 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
 571
 572         if ((periph2 != 0x1) && (periph1 != 0x1) &&
 573                 (periph2 != 0x3) && (periph1 != 0x3))
 574                 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 575
 576         writel(mask480, &anatop->pfd_480_set);
 577         writel(mask528, &anatop->pfd_528_set);
 578         writel(mask480, &anatop->pfd_480_clr);
 579         writel(mask528, &anatop->pfd_528_clr);
 580 }
 581
 582 #ifdef CONFIG_IMX_HDMI
 583 void imx_enable_hdmi_phy(void)
 584 {
 585         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 586         u8 reg;
 587         reg = readb(&hdmi->phy_conf0);
 588         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 589         writeb(reg, &hdmi->phy_conf0);
 590         udelay(3000);
 591         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 592         writeb(reg, &hdmi->phy_conf0);
 593         udelay(3000);
 594         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 595         writeb(reg, &hdmi->phy_conf0);
 596         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 597 }
 598
 599 void imx_setup_hdmi(void)
 600 {
 601         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 602         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 603         int reg, count;
 604         u8 val;
 605
 606         /* Turn on HDMI PHY clock */
 607         reg = readl(&mxc_ccm->CCGR2);
 608         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 609                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 610         writel(reg, &mxc_ccm->CCGR2);
 611         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 612         reg = readl(&mxc_ccm->chsccdr);
 613         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 614                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 615                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 616         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 617                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 618                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 619                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 620         writel(reg, &mxc_ccm->chsccdr);
 621
 622         /* Clear the overflow condition */
 623         if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
 624                 /* TMDS software reset */
 625                 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
 626                 val = readb(&hdmi->fc_invidconf);
 627                 /* Need minimum 3 times to write to clear the register */
 628                 for (count = 0 ; count < 5 ; count++)
 629                         writeb(val, &hdmi->fc_invidconf);
 630         }
 631 }
 632 #endif
 633
 634 #ifdef CONFIG_IMX_BOOTAUX
 635 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 636 {
 637         struct src *src_reg;
 638         u32 stack, pc;
 639
 640         if (!boot_private_data)
 641                 return -EINVAL;
 642
 643         stack = *(u32 *)boot_private_data;
 644         pc = *(u32 *)(boot_private_data + 4);
 645
 646         /* Set the stack and pc to M4 bootROM */
 647         writel(stack, M4_BOOTROM_BASE_ADDR);
 648         writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 649
 650         /* Enable M4 */
 651         src_reg = (struct src *)SRC_BASE_ADDR;
 652         clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
 653                         SRC_SCR_M4_ENABLE_MASK);
 654
 655         return 0;
 656 }
 657
 658 int arch_auxiliary_core_check_up(u32 core_id)
 659 {
 660         struct src *src_reg = (struct src *)SRC_BASE_ADDR;
 661         unsigned val;
 662
 663         val = readl(&src_reg->scr);
 664
 665         if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
 666                 return 0;  /* assert in reset */
 667
 668         return 1;
 669 }
 670 #endif