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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/arm/cpu/armv7/mx6/soc.c
3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
30 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
31 u32 reg
= readl(&anatop
->digprog_sololite
);
32 u32 type
= ((reg
>> 16) & 0xff);
34 if (type
!= MXC_CPU_MX6SL
) {
35 reg
= readl(&anatop
->digprog
);
36 type
= ((reg
>> 16) & 0xff);
37 if (type
== MXC_CPU_MX6DL
) {
38 struct scu_regs
*scu
= (struct scu_regs
*)SCU_BASE_ADDR
;
39 u32 cfg
= readl(&scu
->config
) & 3;
42 type
= MXC_CPU_MX6SOLO
;
45 reg
&= 0xff; /* mx6 silicon revision */
46 return (type
<< 12) | (reg
+ 0x10);
49 #ifdef CONFIG_REVISION_TAG
50 u32 __weak
get_board_rev(void)
52 u32 cpurev
= get_cpu_rev();
53 u32 type
= ((cpurev
>> 12) & 0xff);
54 if (type
== MXC_CPU_MX6SOLO
)
55 cpurev
= (MXC_CPU_MX6DL
) << 12 | (cpurev
& 0xFFF);
63 struct aipstz_regs
*aips1
, *aips2
;
65 aips1
= (struct aipstz_regs
*)AIPS1_BASE_ADDR
;
66 aips2
= (struct aipstz_regs
*)AIPS2_BASE_ADDR
;
69 * Set all MPROTx to be non-bufferable, trusted for R/W,
70 * not forced to user-mode.
72 writel(0x77777777, &aips1
->mprot0
);
73 writel(0x77777777, &aips1
->mprot1
);
74 writel(0x77777777, &aips2
->mprot0
);
75 writel(0x77777777, &aips2
->mprot1
);
78 * Set all OPACRx to be non-bufferable, not require
79 * supervisor privilege level for access,allow for
80 * write access and untrusted master access.
82 writel(0x00000000, &aips1
->opacr0
);
83 writel(0x00000000, &aips1
->opacr1
);
84 writel(0x00000000, &aips1
->opacr2
);
85 writel(0x00000000, &aips1
->opacr3
);
86 writel(0x00000000, &aips1
->opacr4
);
87 writel(0x00000000, &aips2
->opacr0
);
88 writel(0x00000000, &aips2
->opacr1
);
89 writel(0x00000000, &aips2
->opacr2
);
90 writel(0x00000000, &aips2
->opacr3
);
91 writel(0x00000000, &aips2
->opacr4
);
97 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
98 * them to the specified millivolt level.
99 * Possible values are from 0.725V to 1.450V in steps of
102 void set_vddsoc(u32 mv
)
104 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
105 u32 val
, reg
= readl(&anatop
->reg_core
);
108 val
= 0x00; /* Power gated off */
110 val
= 0x1F; /* Power FET switched full on. No regulation */
112 val
= (mv
- 700) / 25;
115 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
116 * and set them to the calculated value (0.7V + val * 0.25V)
118 reg
= (reg
& ~(0x1F << 18)) | (val
<< 18);
119 writel(reg
, &anatop
->reg_core
);
122 static void imx_set_wdog_powerdown(bool enable
)
124 struct wdog_regs
*wdog1
= (struct wdog_regs
*)WDOG1_BASE_ADDR
;
125 struct wdog_regs
*wdog2
= (struct wdog_regs
*)WDOG2_BASE_ADDR
;
127 /* Write to the PDE (Power Down Enable) bit */
128 writew(enable
, &wdog1
->wmcr
);
129 writew(enable
, &wdog2
->wmcr
);
132 int arch_cpu_init(void)
136 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
138 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
140 #ifdef CONFIG_APBH_DMA
148 #ifndef CONFIG_SYS_DCACHE_OFF
149 void enable_caches(void)
151 /* Enable D-cache. I-cache is already enabled in start.S */
156 #if defined(CONFIG_FEC_MXC)
157 void imx_get_mac_from_fuse(int dev_id
, unsigned char *mac
)
159 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
160 struct fuse_bank
*bank
= &ocotp
->bank
[4];
161 struct fuse_bank4_regs
*fuse
=
162 (struct fuse_bank4_regs
*)bank
->fuse_regs
;
164 u32 value
= readl(&fuse
->mac_addr_high
);
165 mac
[0] = (value
>> 8);
168 value
= readl(&fuse
->mac_addr_low
);
169 mac
[2] = value
>> 24 ;
170 mac
[3] = value
>> 16 ;
171 mac
[4] = value
>> 8 ;
177 void boot_mode_apply(unsigned cfg_val
)
180 struct src
*psrc
= (struct src
*)SRC_BASE_ADDR
;
181 writel(cfg_val
, &psrc
->gpr9
);
182 reg
= readl(&psrc
->gpr10
);
187 writel(reg
, &psrc
->gpr10
);
190 * cfg_val will be used for
191 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
192 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
193 * to SBMR1, which will determine the boot device.
195 const struct boot_mode soc_boot_modes
[] = {
196 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
197 /* reserved value should start rom usb */
198 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
199 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
200 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
201 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
202 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
203 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
204 /* 4 bit bus width */
205 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
206 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
207 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
208 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},