3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
18 #include <asm/imx-common/hab.h>
20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h>
23 #include <imx_thermal.h>
40 #if defined(CONFIG_IMX_THERMAL)
41 static const struct imx_thermal_plat imx6_thermal_plat
= {
42 .regs
= (void *)ANATOP_BASE_ADDR
,
47 U_BOOT_DEVICE(imx6_thermal
) = {
48 .name
= "imx_thermal",
49 .platdata
= &imx6_thermal_plat
,
53 #if defined(CONFIG_SECURE_BOOT)
54 struct imx_sec_config_fuse_t
const imx_sec_config_fuse
= {
62 struct scu_regs
*scu
= (struct scu_regs
*)SCU_BASE_ADDR
;
63 return readl(&scu
->config
) & 3;
68 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
69 u32 reg
= readl(&anatop
->digprog_sololite
);
70 u32 type
= ((reg
>> 16) & 0xff);
73 if (type
!= MXC_CPU_MX6SL
) {
74 reg
= readl(&anatop
->digprog
);
75 struct scu_regs
*scu
= (struct scu_regs
*)SCU_BASE_ADDR
;
76 cfg
= readl(&scu
->config
) & 3;
77 type
= ((reg
>> 16) & 0xff);
78 if (type
== MXC_CPU_MX6DL
) {
80 type
= MXC_CPU_MX6SOLO
;
83 if (type
== MXC_CPU_MX6Q
) {
89 major
= ((reg
>> 8) & 0xff);
91 ((type
== MXC_CPU_MX6Q
) || (type
== MXC_CPU_MX6D
))) {
97 reg
&= 0xff; /* mx6 silicon revision */
98 return (type
<< 12) | (reg
+ (0x10 * (major
+ 1)));
102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
103 * defines a 2-bit SPEED_GRADING
105 #define OCOTP_CFG3_SPEED_SHIFT 16
106 #define OCOTP_CFG3_SPEED_800MHZ 0
107 #define OCOTP_CFG3_SPEED_850MHZ 1
108 #define OCOTP_CFG3_SPEED_1GHZ 2
109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
111 u32
get_cpu_speed_grade_hz(void)
113 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
114 struct fuse_bank
*bank
= &ocotp
->bank
[0];
115 struct fuse_bank0_regs
*fuse
=
116 (struct fuse_bank0_regs
*)bank
->fuse_regs
;
119 val
= readl(&fuse
->cfg3
);
120 val
>>= OCOTP_CFG3_SPEED_SHIFT
;
124 /* Valid for IMX6DQ */
125 case OCOTP_CFG3_SPEED_1P2GHZ
:
126 if (is_cpu_type(MXC_CPU_MX6Q
) || is_cpu_type(MXC_CPU_MX6D
))
128 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
129 case OCOTP_CFG3_SPEED_1GHZ
:
131 /* Valid for IMX6DQ */
132 case OCOTP_CFG3_SPEED_850MHZ
:
133 if (is_cpu_type(MXC_CPU_MX6Q
) || is_cpu_type(MXC_CPU_MX6D
))
135 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
136 case OCOTP_CFG3_SPEED_800MHZ
:
143 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
144 * defines a 2-bit Temperature Grade
146 * return temperature grade and min/max temperature in celcius
148 #define OCOTP_MEM0_TEMP_SHIFT 6
150 u32
get_cpu_temp_grade(int *minc
, int *maxc
)
152 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
153 struct fuse_bank
*bank
= &ocotp
->bank
[1];
154 struct fuse_bank1_regs
*fuse
=
155 (struct fuse_bank1_regs
*)bank
->fuse_regs
;
158 val
= readl(&fuse
->mem0
);
159 val
>>= OCOTP_MEM0_TEMP_SHIFT
;
163 if (val
== TEMP_AUTOMOTIVE
) {
166 } else if (val
== TEMP_INDUSTRIAL
) {
169 } else if (val
== TEMP_EXTCOMMERCIAL
) {
180 #ifdef CONFIG_REVISION_TAG
181 u32 __weak
get_board_rev(void)
183 u32 cpurev
= get_cpu_rev();
184 u32 type
= ((cpurev
>> 12) & 0xff);
185 if (type
== MXC_CPU_MX6SOLO
)
186 cpurev
= (MXC_CPU_MX6DL
) << 12 | (cpurev
& 0xFFF);
188 if (type
== MXC_CPU_MX6D
)
189 cpurev
= (MXC_CPU_MX6Q
) << 12 | (cpurev
& 0xFFF);
195 static void clear_ldo_ramp(void)
197 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
200 /* ROM may modify LDO ramp up time according to fuse setting, so in
201 * order to be in the safe side we neeed to reset these settings to
202 * match the reset value: 0'b00
204 reg
= readl(&anatop
->ana_misc2
);
205 reg
&= ~(0x3f << 24);
206 writel(reg
, &anatop
->ana_misc2
);
210 * Set the PMU_REG_CORE register
212 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
213 * Possible values are from 0.725V to 1.450V in steps of
216 static int set_ldo_voltage(enum ldo_reg ldo
, u32 mv
)
218 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
219 u32 val
, step
, old
, reg
= readl(&anatop
->reg_core
);
223 val
= 0x00; /* Power gated off */
225 val
= 0x1F; /* Power FET switched full on. No regulation */
227 val
= (mv
- 700) / 25;
245 old
= (reg
& (0x1F << shift
)) >> shift
;
246 step
= abs(val
- old
);
250 reg
= (reg
& ~(0x1F << shift
)) | (val
<< shift
);
251 writel(reg
, &anatop
->reg_core
);
254 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
262 static void set_ahb_rate(u32 val
)
264 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
267 div
= get_periph_clk() / val
- 1;
268 reg
= readl(&mxc_ccm
->cbcdr
);
270 writel((reg
& (~MXC_CCM_CBCDR_AHB_PODF_MASK
)) |
271 (div
<< MXC_CCM_CBCDR_AHB_PODF_OFFSET
), &mxc_ccm
->cbcdr
);
274 static void clear_mmdc_ch_mask(void)
276 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
278 reg
= readl(&mxc_ccm
->ccdr
);
280 /* Clear MMDC channel mask */
281 reg
&= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK
| MXC_CCM_CCDR_MMDC_CH0_HS_MASK
);
282 writel(reg
, &mxc_ccm
->ccdr
);
285 static void init_bandgap(void)
287 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
289 * Ensure the bandgap has stabilized.
291 while (!(readl(&anatop
->ana_misc0
) & 0x80))
294 * For best noise performance of the analog blocks using the
295 * outputs of the bandgap, the reftop_selfbiasoff bit should
298 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF
, &anatop
->ana_misc0_set
);
303 static void set_preclk_from_osc(void)
305 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
308 reg
= readl(&mxc_ccm
->cscmr1
);
309 reg
|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
;
310 writel(reg
, &mxc_ccm
->cscmr1
);
314 int arch_cpu_init(void)
318 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
319 clear_mmdc_ch_mask();
322 * Disable self-bias circuit in the analog bandap.
323 * The self-bias circuit is used by the bandgap during startup.
324 * This bit should be set after the bandgap has initialized.
329 * When low freq boot is enabled, ROM will not set AHB
330 * freq, so we need to ensure AHB freq is 132MHz in such
333 if (mxc_get_clock(MXC_ARM_CLK
) == 396000000)
334 set_ahb_rate(132000000);
336 /* Set perclk to source from OSC 24MHz */
337 #if defined(CONFIG_MX6SL)
338 set_preclk_from_osc();
341 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
343 #ifdef CONFIG_APBH_DMA
353 #ifdef CONFIG_ENV_IS_IN_MMC
354 __weak
int board_mmc_get_env_dev(int devno
)
356 return CONFIG_SYS_MMC_ENV_DEV
;
359 static int mmc_get_boot_dev(void)
361 struct src
*src_regs
= (struct src
*)SRC_BASE_ADDR
;
362 u32 soc_sbmr
= readl(&src_regs
->sbmr1
);
368 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
369 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
370 * i.MX6SL/SX/UL has same layout.
372 bootsel
= (soc_sbmr
& 0x000000FF) >> 6;
374 /* No boot from sd/mmc */
378 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
379 devno
= (soc_sbmr
& 0x00001800) >> 11;
384 int mmc_get_env_dev(void)
386 int devno
= mmc_get_boot_dev();
388 /* If not boot from sd/mmc, use default value */
390 return CONFIG_SYS_MMC_ENV_DEV
;
392 return board_mmc_get_env_dev(devno
);
395 #ifdef CONFIG_SYS_MMC_ENV_PART
396 __weak
int board_mmc_get_env_part(int devno
)
398 return CONFIG_SYS_MMC_ENV_PART
;
401 uint
mmc_get_env_part(struct mmc
*mmc
)
403 int devno
= mmc_get_boot_dev();
405 /* If not boot from sd/mmc, use default value */
407 return CONFIG_SYS_MMC_ENV_PART
;
409 return board_mmc_get_env_part(devno
);
414 int board_postclk_init(void)
416 set_ldo_voltage(LDO_SOC
, 1175); /* Set VDDSOC to 1.175V */
421 #if defined(CONFIG_FEC_MXC)
422 void imx_get_mac_from_fuse(int dev_id
, unsigned char *mac
)
424 struct ocotp_regs
*ocotp
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
425 struct fuse_bank
*bank
= &ocotp
->bank
[4];
426 struct fuse_bank4_regs
*fuse
=
427 (struct fuse_bank4_regs
*)bank
->fuse_regs
;
429 if ((is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
)) &&
431 u32 value
= readl(&fuse
->mac_addr2
);
432 mac
[0] = value
>> 24 ;
433 mac
[1] = value
>> 16 ;
434 mac
[2] = value
>> 8 ;
437 value
= readl(&fuse
->mac_addr1
);
438 mac
[4] = value
>> 24 ;
439 mac
[5] = value
>> 16 ;
442 u32 value
= readl(&fuse
->mac_addr1
);
443 mac
[0] = (value
>> 8);
446 value
= readl(&fuse
->mac_addr0
);
447 mac
[2] = value
>> 24 ;
448 mac
[3] = value
>> 16 ;
449 mac
[4] = value
>> 8 ;
457 * cfg_val will be used for
458 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
459 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
460 * instead of SBMR1 to determine the boot device.
462 const struct boot_mode soc_boot_modes
[] = {
463 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
464 /* reserved value should start rom usb */
465 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
466 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
467 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
468 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
469 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
470 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
471 /* 4 bit bus width */
472 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
473 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
474 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
475 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
479 void reset_misc(void)
481 #ifdef CONFIG_VIDEO_MXS
488 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
489 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
492 u32 reg
, periph1
, periph2
;
494 if (is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
))
497 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
498 * to make sure PFD is working right, otherwise, PFDs may
499 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
500 * workaround in ROM code, as bus clock need it
503 mask480
= ANATOP_PFD_CLKGATE_MASK(0) |
504 ANATOP_PFD_CLKGATE_MASK(1) |
505 ANATOP_PFD_CLKGATE_MASK(2) |
506 ANATOP_PFD_CLKGATE_MASK(3);
507 mask528
= ANATOP_PFD_CLKGATE_MASK(1) |
508 ANATOP_PFD_CLKGATE_MASK(3);
510 reg
= readl(&ccm
->cbcmr
);
511 periph2
= ((reg
& MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
)
512 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
);
513 periph1
= ((reg
& MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
)
514 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
);
516 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
517 if ((periph2
!= 0x2) && (periph1
!= 0x2))
518 mask528
|= ANATOP_PFD_CLKGATE_MASK(0);
520 if ((periph2
!= 0x1) && (periph1
!= 0x1) &&
521 (periph2
!= 0x3) && (periph1
!= 0x3))
522 mask528
|= ANATOP_PFD_CLKGATE_MASK(2);
524 writel(mask480
, &anatop
->pfd_480_set
);
525 writel(mask528
, &anatop
->pfd_528_set
);
526 writel(mask480
, &anatop
->pfd_480_clr
);
527 writel(mask528
, &anatop
->pfd_528_clr
);
530 #ifdef CONFIG_IMX_HDMI
531 void imx_enable_hdmi_phy(void)
533 struct hdmi_regs
*hdmi
= (struct hdmi_regs
*)HDMI_ARB_BASE_ADDR
;
535 reg
= readb(&hdmi
->phy_conf0
);
536 reg
|= HDMI_PHY_CONF0_PDZ_MASK
;
537 writeb(reg
, &hdmi
->phy_conf0
);
539 reg
|= HDMI_PHY_CONF0_ENTMDS_MASK
;
540 writeb(reg
, &hdmi
->phy_conf0
);
542 reg
|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK
;
543 writeb(reg
, &hdmi
->phy_conf0
);
544 writeb(HDMI_MC_PHYRSTZ_ASSERT
, &hdmi
->mc_phyrstz
);
547 void imx_setup_hdmi(void)
549 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
550 struct hdmi_regs
*hdmi
= (struct hdmi_regs
*)HDMI_ARB_BASE_ADDR
;
553 /* Turn on HDMI PHY clock */
554 reg
= readl(&mxc_ccm
->CCGR2
);
555 reg
|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|
556 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK
;
557 writel(reg
, &mxc_ccm
->CCGR2
);
558 writeb(HDMI_MC_PHYRSTZ_DEASSERT
, &hdmi
->mc_phyrstz
);
559 reg
= readl(&mxc_ccm
->chsccdr
);
560 reg
&= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|
561 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|
562 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK
);
563 reg
|= (CHSCCDR_PODF_DIVIDE_BY_3
564 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET
)
565 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
566 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET
);
567 writel(reg
, &mxc_ccm
->chsccdr
);
571 #ifdef CONFIG_IMX_BOOTAUX
572 int arch_auxiliary_core_up(u32 core_id
, u32 boot_private_data
)
577 if (!boot_private_data
)
580 stack
= *(u32
*)boot_private_data
;
581 pc
= *(u32
*)(boot_private_data
+ 4);
583 /* Set the stack and pc to M4 bootROM */
584 writel(stack
, M4_BOOTROM_BASE_ADDR
);
585 writel(pc
, M4_BOOTROM_BASE_ADDR
+ 4);
588 src_reg
= (struct src
*)SRC_BASE_ADDR
;
589 clrsetbits_le32(&src_reg
->scr
, SRC_SCR_M4C_NON_SCLR_RST_MASK
,
590 SRC_SCR_M4_ENABLE_MASK
);
595 int arch_auxiliary_core_check_up(u32 core_id
)
597 struct src
*src_reg
= (struct src
*)SRC_BASE_ADDR
;
600 val
= readl(&src_reg
->scr
);
602 if (val
& SRC_SCR_M4C_NON_SCLR_RST_MASK
)
603 return 0; /* assert in reset */