arch/arm/cpu/armv7/omap3/board.c

   1 /*
   2  *
   3  * Common board functions for OMAP3 based boards.
   4  *
   5  * (C) Copyright 2004-2008
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Sunil Kumar <sunilsaini05@gmail.com>
  10  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
  11  *
  12  * Derived from Beagle Board and 3430 SDP code by
  13  *      Richard Woodruff <r-woodruff2@ti.com>
  14  *      Syed Mohammed Khasim <khasim@ti.com>
  15  *
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35 #include <common.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/sys_proto.h>
  38 #include <asm/arch/mem.h>
  39 #include <asm/cache.h>
  40 #include <asm/armv7.h>
  41
  42 /* Declarations */
  43 extern omap3_sysinfo sysinfo;
  44 static void omap3_setup_aux_cr(void);
  45 static void omap3_invalidate_l2_cache_secure(void);
  46
  47 /******************************************************************************
  48  * Routine: delay
  49  * Description: spinning delay to use before udelay works
  50  *****************************************************************************/
  51 static inline void delay(unsigned long loops)
  52 {
  53         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  54                           "bne 1b":"=r" (loops):"0"(loops));
  55 }
  56
  57 /******************************************************************************
  58  * Routine: secure_unlock
  59  * Description: Setup security registers for access
  60  *              (GP Device only)
  61  *****************************************************************************/
  62 void secure_unlock_mem(void)
  63 {
  64         struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
  65         struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
  66         struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
  67         struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
  68         struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
  69
  70         /* Protection Module Register Target APE (PM_RT) */
  71         writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
  72         writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
  73         writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
  74         writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
  75
  76         writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
  77         writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
  78         writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
  79
  80         writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
  81         writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
  82         writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
  83         writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
  84
  85         /* IVA Changes */
  86         writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
  87         writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
  88         writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
  89
  90         /* SDRC region 0 public */
  91         writel(UNLOCK_1, &sms_base->rg_att0);
  92 }
  93
  94 /******************************************************************************
  95  * Routine: secureworld_exit()
  96  * Description: If chip is EMU and boot type is external
  97  *              configure secure registers and exit secure world
  98  *              general use.
  99  *****************************************************************************/
 100 void secureworld_exit()
 101 {
 102         unsigned long i;
 103
 104         /* configrue non-secure access control register */
 105         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 106         /* enabling co-processor CP10 and CP11 accesses in NS world */
 107         __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
 108         /*
 109          * allow allocation of locked TLBs and L2 lines in NS world
 110          * allow use of PLE registers in NS world also
 111          */
 112         __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
 113         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
 114
 115         /* Enable ASA in ACR register */
 116         __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 117         __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
 118         __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 119
 120         /* Exiting secure world */
 121         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
 122         __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
 123         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
 124 }
 125
 126 /******************************************************************************
 127  * Routine: try_unlock_sram()
 128  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 129  *              general use.
 130  *****************************************************************************/
 131 void try_unlock_memory()
 132 {
 133         int mode;
 134         int in_sdram = is_running_in_sdram();
 135
 136         /*
 137          * if GP device unlock device SRAM for general use
 138          * secure code breaks for Secure/Emulation device - HS/E/T
 139          */
 140         mode = get_device_type();
 141         if (mode == GP_DEVICE)
 142                 secure_unlock_mem();
 143
 144         /*
 145          * If device is EMU and boot is XIP external booting
 146          * Unlock firewalls and disable L2 and put chip
 147          * out of secure world
 148          *
 149          * Assuming memories are unlocked by the demon who put us in SDRAM
 150          */
 151         if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
 152             && (!in_sdram)) {
 153                 secure_unlock_mem();
 154                 secureworld_exit();
 155         }
 156
 157         return;
 158 }
 159
 160 /******************************************************************************
 161  * Routine: s_init
 162  * Description: Does early system init of muxing and clocks.
 163  *              - Called path is with SRAM stack.
 164  *****************************************************************************/
 165 void s_init(void)
 166 {
 167         int in_sdram = is_running_in_sdram();
 168
 169         watchdog_init();
 170
 171         try_unlock_memory();
 172
 173         /* Errata workarounds */
 174         omap3_setup_aux_cr();
 175
 176 #ifndef CONFIG_SYS_L2CACHE_OFF
 177         /* Invalidate L2-cache from secure mode */
 178         omap3_invalidate_l2_cache_secure();
 179 #endif
 180
 181         set_muxconf_regs();
 182         delay(100);
 183
 184         prcm_init();
 185
 186         per_clocks_enable();
 187
 188         if (!in_sdram)
 189                 mem_init();
 190 }
 191
 192 /******************************************************************************
 193  * Routine: wait_for_command_complete
 194  * Description: Wait for posting to finish on watchdog
 195  *****************************************************************************/
 196 void wait_for_command_complete(struct watchdog *wd_base)
 197 {
 198         int pending = 1;
 199         do {
 200                 pending = readl(&wd_base->wwps);
 201         } while (pending);
 202 }
 203
 204 /******************************************************************************
 205  * Routine: watchdog_init
 206  * Description: Shut down watch dogs
 207  *****************************************************************************/
 208 void watchdog_init(void)
 209 {
 210         struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
 211         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 212
 213         /*
 214          * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
 215          * either taken care of by ROM (HS/EMU) or not accessible (GP).
 216          * We need to take care of WD2-MPU or take a PRCM reset. WD3
 217          * should not be running and does not generate a PRCM reset.
 218          */
 219
 220         sr32(&prcm_base->fclken_wkup, 5, 1, 1);
 221         sr32(&prcm_base->iclken_wkup, 5, 1, 1);
 222         wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 223
 224         writel(WD_UNLOCK1, &wd2_base->wspr);
 225         wait_for_command_complete(wd2_base);
 226         writel(WD_UNLOCK2, &wd2_base->wspr);
 227 }
 228
 229 /******************************************************************************
 230  * Dummy function to handle errors for EABI incompatibility
 231  *****************************************************************************/
 232 void abort(void)
 233 {
 234 }
 235
 236 #ifdef CONFIG_NAND_OMAP_GPMC
 237 /******************************************************************************
 238  * OMAP3 specific command to switch between NAND HW and SW ecc
 239  *****************************************************************************/
 240 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 241 {
 242         if (argc != 2)
 243                 goto usage;
 244         if (strncmp(argv[1], "hw", 2) == 0)
 245                 omap_nand_switch_ecc(1);
 246         else if (strncmp(argv[1], "sw", 2) == 0)
 247                 omap_nand_switch_ecc(0);
 248         else
 249                 goto usage;
 250
 251         return 0;
 252
 253 usage:
 254         printf ("Usage: nandecc %s\n", cmdtp->usage);
 255         return 1;
 256 }
 257
 258 U_BOOT_CMD(
 259         nandecc, 2, 1,  do_switch_ecc,
 260         "switch OMAP3 NAND ECC calculation algorithm",
 261         "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
 262 );
 263
 264 #endif /* CONFIG_NAND_OMAP_GPMC */
 265
 266 #ifdef CONFIG_DISPLAY_BOARDINFO
 267 /**
 268  * Print board information
 269  */
 270 int checkboard (void)
 271 {
 272         char *mem_s ;
 273
 274         if (is_mem_sdr())
 275                 mem_s = "mSDR";
 276         else
 277                 mem_s = "LPDDR";
 278
 279         printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
 280                         sysinfo.nand_string);
 281
 282         return 0;
 283 }
 284 #endif  /* CONFIG_DISPLAY_BOARDINFO */
 285
 286 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 287 {
 288         u32 i, num_params = *parameters;
 289         u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
 290
 291         /*
 292          * copy the parameters to an un-cached area to avoid coherency
 293          * issues
 294          */
 295         for (i = 0; i < num_params; i++) {
 296                 __raw_writel(*parameters, sram_scratch_space);
 297                 parameters++;
 298                 sram_scratch_space++;
 299         }
 300
 301         /* Now make the PPA call */
 302         do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 303 }
 304
 305 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 306 {
 307         u32 acr;
 308
 309         /* Read ACR */
 310         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 311         acr &= ~clear_bits;
 312         acr |= set_bits;
 313
 314         if (get_device_type() == GP_DEVICE) {
 315                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
 316                                        acr);
 317         } else {
 318                 struct emu_hal_params emu_romcode_params;
 319                 emu_romcode_params.num_params = 1;
 320                 emu_romcode_params.param1 = acr;
 321                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
 322                                        (u32 *)&emu_romcode_params);
 323         }
 324 }
 325
 326 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 327 {
 328         u32 acr;
 329
 330         /* Read ACR */
 331         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 332         acr &= ~clear_bits;
 333         acr |= set_bits;
 334
 335         /* Write ACR - affects non-secure banked bits */
 336         asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 337 }
 338
 339 static void omap3_setup_aux_cr(void)
 340 {
 341         /* Workaround for Cortex-A8 errata: #454179 #430973
 342          *      Set "IBE" bit
 343          *      Set "Disable Brach Size Mispredicts" bit
 344          * Workaround for erratum #621766
 345          *      Enable L1NEON bit
 346          * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
 347          */
 348         omap3_update_aux_cr_secure(0xE0, 0);
 349 }
 350
 351 #ifndef CONFIG_SYS_L2CACHE_OFF
 352 /* Invalidate the entire L2 cache from secure mode */
 353 static void omap3_invalidate_l2_cache_secure(void)
 354 {
 355         if (get_device_type() == GP_DEVICE) {
 356                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
 357                                       0);
 358         } else {
 359                 struct emu_hal_params emu_romcode_params;
 360                 emu_romcode_params.num_params = 1;
 361                 emu_romcode_params.param1 = 0;
 362                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
 363                                        (u32 *)&emu_romcode_params);
 364         }
 365 }
 366
 367 void v7_outer_cache_enable(void)
 368 {
 369         /* Set L2EN */
 370         omap3_update_aux_cr_secure(0x2, 0);
 371
 372         /*
 373          * On some revisions L2EN bit is banked on some revisions it's not
 374          * No harm in setting both banked bits(in fact this is required
 375          * by an erratum)
 376          */
 377         omap3_update_aux_cr(0x2, 0);
 378 }
 379
 380 void v7_outer_cache_disable(void)
 381 {
 382         /* Clear L2EN */
 383         omap3_update_aux_cr_secure(0, 0x2);
 384
 385         /*
 386          * On some revisions L2EN bit is banked on some revisions it's not
 387          * No harm in clearing both banked bits(in fact this is required
 388          * by an erratum)
 389          */
 390         omap3_update_aux_cr(0, 0x2);
 391 }
 392 #endif