arch/arm/cpu/armv7/omap3/board.c

   1 /*
   2  *
   3  * Common board functions for OMAP3 based boards.
   4  *
   5  * (C) Copyright 2004-2008
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Sunil Kumar <sunilsaini05@gmail.com>
  10  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
  11  *
  12  * Derived from Beagle Board and 3430 SDP code by
  13  *      Richard Woodruff <r-woodruff2@ti.com>
  14  *      Syed Mohammed Khasim <khasim@ti.com>
  15  *
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35 #include <common.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/sys_proto.h>
  38 #include <asm/arch/mem.h>
  39 #include <asm/cache.h>
  40 #include <asm/armv7.h>
  41 #include <asm/arch/gpio.h>
  42 #include <asm/omap_common.h>
  43 #include <i2c.h>
  44 #include <linux/compiler.h>
  45
  46 /* Declarations */
  47 extern omap3_sysinfo sysinfo;
  48 static void omap3_setup_aux_cr(void);
  49 static void omap3_invalidate_l2_cache_secure(void);
  50
  51 static const struct gpio_bank gpio_bank_34xx[6] = {
  52         { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
  53         { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
  54         { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
  55         { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
  56         { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
  57         { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
  58 };
  59
  60 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 /*
  64 * We use static variables because global data is not ready yet.
  65 * Initialized data is available in SPL right from the beginning.
  66 * We would not typically need to save these parameters in regular
  67 * U-Boot. This is needed only in SPL at the moment.
  68 */
  69 u32 omap3_boot_device = BOOT_DEVICE_NAND;
  70
  71 /* auto boot mode detection is not possible for OMAP3 - hard code */
  72 u32 omap_boot_mode(void)
  73 {
  74         switch (spl_boot_device()) {
  75         case BOOT_DEVICE_MMC2:
  76                 return MMCSD_MODE_RAW;
  77         case BOOT_DEVICE_MMC1:
  78                 return MMCSD_MODE_FAT;
  79                 break;
  80         case BOOT_DEVICE_NAND:
  81                 return NAND_MODE_HW_ECC;
  82                 break;
  83         default:
  84                 puts("spl: ERROR:  unknown device - can't select boot mode\n");
  85                 hang();
  86         }
  87 }
  88
  89 u32 spl_boot_device(void)
  90 {
  91         return omap3_boot_device;
  92 }
  93
  94 void spl_board_init(void)
  95 {
  96 #ifdef CONFIG_SPL_I2C_SUPPORT
  97         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  98 #endif
  99 }
 100 #endif /* CONFIG_SPL_BUILD */
 101
 102
 103 /******************************************************************************
 104  * Routine: secure_unlock
 105  * Description: Setup security registers for access
 106  *              (GP Device only)
 107  *****************************************************************************/
 108 void secure_unlock_mem(void)
 109 {
 110         struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
 111         struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
 112         struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
 113         struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
 114         struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 115
 116         /* Protection Module Register Target APE (PM_RT) */
 117         writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
 118         writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
 119         writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
 120         writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
 121
 122         writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
 123         writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
 124         writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
 125
 126         writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
 127         writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
 128         writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
 129         writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
 130
 131         /* IVA Changes */
 132         writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
 133         writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
 134         writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
 135
 136         /* SDRC region 0 public */
 137         writel(UNLOCK_1, &sms_base->rg_att0);
 138 }
 139
 140 /******************************************************************************
 141  * Routine: secureworld_exit()
 142  * Description: If chip is EMU and boot type is external
 143  *              configure secure registers and exit secure world
 144  *              general use.
 145  *****************************************************************************/
 146 void secureworld_exit()
 147 {
 148         unsigned long i;
 149
 150         /* configure non-secure access control register */
 151         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 152         /* enabling co-processor CP10 and CP11 accesses in NS world */
 153         __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
 154         /*
 155          * allow allocation of locked TLBs and L2 lines in NS world
 156          * allow use of PLE registers in NS world also
 157          */
 158         __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
 159         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
 160
 161         /* Enable ASA in ACR register */
 162         __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 163         __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
 164         __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 165
 166         /* Exiting secure world */
 167         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
 168         __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
 169         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
 170 }
 171
 172 /******************************************************************************
 173  * Routine: try_unlock_sram()
 174  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 175  *              general use.
 176  *****************************************************************************/
 177 void try_unlock_memory()
 178 {
 179         int mode;
 180         int in_sdram = is_running_in_sdram();
 181
 182         /*
 183          * if GP device unlock device SRAM for general use
 184          * secure code breaks for Secure/Emulation device - HS/E/T
 185          */
 186         mode = get_device_type();
 187         if (mode == GP_DEVICE)
 188                 secure_unlock_mem();
 189
 190         /*
 191          * If device is EMU and boot is XIP external booting
 192          * Unlock firewalls and disable L2 and put chip
 193          * out of secure world
 194          *
 195          * Assuming memories are unlocked by the demon who put us in SDRAM
 196          */
 197         if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
 198             && (!in_sdram)) {
 199                 secure_unlock_mem();
 200                 secureworld_exit();
 201         }
 202
 203         return;
 204 }
 205
 206 /******************************************************************************
 207  * Routine: s_init
 208  * Description: Does early system init of muxing and clocks.
 209  *              - Called path is with SRAM stack.
 210  *****************************************************************************/
 211 void s_init(void)
 212 {
 213         int in_sdram = is_running_in_sdram();
 214
 215         watchdog_init();
 216
 217         try_unlock_memory();
 218
 219         /* Errata workarounds */
 220         omap3_setup_aux_cr();
 221
 222 #ifndef CONFIG_SYS_L2CACHE_OFF
 223         /* Invalidate L2-cache from secure mode */
 224         omap3_invalidate_l2_cache_secure();
 225 #endif
 226
 227         set_muxconf_regs();
 228         sdelay(100);
 229
 230         prcm_init();
 231
 232         per_clocks_enable();
 233
 234 #ifdef CONFIG_USB_EHCI_OMAP
 235         ehci_clocks_enable();
 236 #endif
 237
 238 #ifdef CONFIG_SPL_BUILD
 239         preloader_console_init();
 240
 241         timer_init();
 242 #endif
 243
 244         if (!in_sdram)
 245                 mem_init();
 246 }
 247
 248 /*
 249  * Routine: misc_init_r
 250  * Description: A basic misc_init_r that just displays the die ID
 251  */
 252 int __weak misc_init_r(void)
 253 {
 254         dieid_num_r();
 255
 256         return 0;
 257 }
 258
 259 /******************************************************************************
 260  * Routine: wait_for_command_complete
 261  * Description: Wait for posting to finish on watchdog
 262  *****************************************************************************/
 263 void wait_for_command_complete(struct watchdog *wd_base)
 264 {
 265         int pending = 1;
 266         do {
 267                 pending = readl(&wd_base->wwps);
 268         } while (pending);
 269 }
 270
 271 /******************************************************************************
 272  * Routine: watchdog_init
 273  * Description: Shut down watch dogs
 274  *****************************************************************************/
 275 void watchdog_init(void)
 276 {
 277         struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
 278         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 279
 280         /*
 281          * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
 282          * either taken care of by ROM (HS/EMU) or not accessible (GP).
 283          * We need to take care of WD2-MPU or take a PRCM reset. WD3
 284          * should not be running and does not generate a PRCM reset.
 285          */
 286
 287         sr32(&prcm_base->fclken_wkup, 5, 1, 1);
 288         sr32(&prcm_base->iclken_wkup, 5, 1, 1);
 289         wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 290
 291         writel(WD_UNLOCK1, &wd2_base->wspr);
 292         wait_for_command_complete(wd2_base);
 293         writel(WD_UNLOCK2, &wd2_base->wspr);
 294 }
 295
 296 /******************************************************************************
 297  * Dummy function to handle errors for EABI incompatibility
 298  *****************************************************************************/
 299 void abort(void)
 300 {
 301 }
 302
 303 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
 304 /******************************************************************************
 305  * OMAP3 specific command to switch between NAND HW and SW ecc
 306  *****************************************************************************/
 307 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 308 {
 309         if (argc != 2)
 310                 goto usage;
 311         if (strncmp(argv[1], "hw", 2) == 0)
 312                 omap_nand_switch_ecc(1);
 313         else if (strncmp(argv[1], "sw", 2) == 0)
 314                 omap_nand_switch_ecc(0);
 315         else
 316                 goto usage;
 317
 318         return 0;
 319
 320 usage:
 321         printf ("Usage: nandecc %s\n", cmdtp->usage);
 322         return 1;
 323 }
 324
 325 U_BOOT_CMD(
 326         nandecc, 2, 1,  do_switch_ecc,
 327         "switch OMAP3 NAND ECC calculation algorithm",
 328         "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
 329 );
 330
 331 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
 332
 333 #ifdef CONFIG_DISPLAY_BOARDINFO
 334 /**
 335  * Print board information
 336  */
 337 int checkboard (void)
 338 {
 339         char *mem_s ;
 340
 341         if (is_mem_sdr())
 342                 mem_s = "mSDR";
 343         else
 344                 mem_s = "LPDDR";
 345
 346         printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
 347                         sysinfo.nand_string);
 348
 349         return 0;
 350 }
 351 #endif  /* CONFIG_DISPLAY_BOARDINFO */
 352
 353 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 354 {
 355         u32 i, num_params = *parameters;
 356         u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
 357
 358         /*
 359          * copy the parameters to an un-cached area to avoid coherency
 360          * issues
 361          */
 362         for (i = 0; i < num_params; i++) {
 363                 __raw_writel(*parameters, sram_scratch_space);
 364                 parameters++;
 365                 sram_scratch_space++;
 366         }
 367
 368         /* Now make the PPA call */
 369         do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 370 }
 371
 372 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 373 {
 374         u32 acr;
 375
 376         /* Read ACR */
 377         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 378         acr &= ~clear_bits;
 379         acr |= set_bits;
 380
 381         if (get_device_type() == GP_DEVICE) {
 382                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
 383                                        acr);
 384         } else {
 385                 struct emu_hal_params emu_romcode_params;
 386                 emu_romcode_params.num_params = 1;
 387                 emu_romcode_params.param1 = acr;
 388                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
 389                                        (u32 *)&emu_romcode_params);
 390         }
 391 }
 392
 393 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 394 {
 395         u32 acr;
 396
 397         /* Read ACR */
 398         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 399         acr &= ~clear_bits;
 400         acr |= set_bits;
 401
 402         /* Write ACR - affects non-secure banked bits */
 403         asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 404 }
 405
 406 static void omap3_setup_aux_cr(void)
 407 {
 408         /* Workaround for Cortex-A8 errata: #454179 #430973
 409          *      Set "IBE" bit
 410          *      Set "Disable Branch Size Mispredicts" bit
 411          * Workaround for erratum #621766
 412          *      Enable L1NEON bit
 413          * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
 414          */
 415         omap3_update_aux_cr_secure(0xE0, 0);
 416 }
 417
 418 #ifndef CONFIG_SYS_L2CACHE_OFF
 419 /* Invalidate the entire L2 cache from secure mode */
 420 static void omap3_invalidate_l2_cache_secure(void)
 421 {
 422         if (get_device_type() == GP_DEVICE) {
 423                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
 424                                       0);
 425         } else {
 426                 struct emu_hal_params emu_romcode_params;
 427                 emu_romcode_params.num_params = 1;
 428                 emu_romcode_params.param1 = 0;
 429                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
 430                                        (u32 *)&emu_romcode_params);
 431         }
 432 }
 433
 434 void v7_outer_cache_enable(void)
 435 {
 436         /* Set L2EN */
 437         omap3_update_aux_cr_secure(0x2, 0);
 438
 439         /*
 440          * On some revisions L2EN bit is banked on some revisions it's not
 441          * No harm in setting both banked bits(in fact this is required
 442          * by an erratum)
 443          */
 444         omap3_update_aux_cr(0x2, 0);
 445 }
 446
 447 void omap3_outer_cache_disable(void)
 448 {
 449         /* Clear L2EN */
 450         omap3_update_aux_cr_secure(0, 0x2);
 451
 452         /*
 453          * On some revisions L2EN bit is banked on some revisions it's not
 454          * No harm in clearing both banked bits(in fact this is required
 455          * by an erratum)
 456          */
 457         omap3_update_aux_cr(0, 0x2);
 458 }
 459 #endif
 460
 461 #ifndef CONFIG_SYS_DCACHE_OFF
 462 void enable_caches(void)
 463 {
 464         /* Enable D-cache. I-cache is already enabled in start.S */
 465         dcache_enable();
 466 }
 467 #endif