arch/arm/cpu/armv7/omap3/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2008
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Initial Code by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Syed Mohammed Khasim <khasim@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/arch/mem.h>
  33 #include <asm/arch/clocks_omap3.h>
  34
  35 _TEXT_BASE:
  36         .word   CONFIG_SYS_TEXT_BASE    /* sdram load addr from config.mk */
  37
  38 .global save_boot_params
  39 save_boot_params:
  40 #ifdef CONFIG_SPL_BUILD
  41         ldr     r4, =omap3_boot_device
  42         ldr     r5, [r0, #0x4]
  43         and     r5, r5, #0xff
  44         str     r5, [r4]
  45 #endif
  46         bx      lr
  47
  48 .global omap3_gp_romcode_call
  49 omap3_gp_romcode_call:
  50         PUSH {r4-r12, lr} @ Save all registers from ROM code!
  51         MOV r12, r0     @ Copy the Service ID in R12
  52         MOV r0, r1      @ Copy parameter to R0
  53         mcr     p15, 0, r0, c7, c10, 4  @ DSB
  54         mcr     p15, 0, r0, c7, c10, 5  @ DMB
  55         .word   0xe1600070      @ SMC #0 to enter monitor - hand assembled
  56                                 @ because we use -march=armv5
  57         POP {r4-r12, pc}
  58
  59 /*
  60  * Funtion for making PPA HAL API calls in secure devices
  61  * Input:
  62  *      R0 - Service ID
  63  *      R1 - paramer list
  64  */
  65 .global do_omap3_emu_romcode_call
  66 do_omap3_emu_romcode_call:
  67         PUSH {r4-r12, lr} @ Save all registers from ROM code!
  68         MOV r12, r0     @ Copy the Secure Service ID in R12
  69         MOV r3, r1      @ Copy the pointer to va_list in R3
  70         MOV r1, #0      @ Process ID - 0
  71         MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL       @ Copy the pointer
  72                                                         @ to va_list in R3
  73         MOV r6, #0xFF   @ Indicate new Task call
  74         mcr     p15, 0, r0, c7, c10, 4  @ DSB
  75         mcr     p15, 0, r0, c7, c10, 5  @ DMB
  76         .word   0xe1600071      @ SMC #1 to call PPA service - hand assembled
  77                                 @ because we use -march=armv5
  78         POP {r4-r12, pc}
  79
  80 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
  81 /**************************************************************************
  82  * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  83  * R1 = SRAM destination address.
  84  *************************************************************************/
  85 .global cpy_clk_code
  86  cpy_clk_code:
  87         /* Copy DPLL code into SRAM */
  88         adr     r0, go_to_speed         /* get addr of clock setting code */
  89         mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
  90         mov     r1, r1                  /* r1 <- dest address (passed in) */
  91         add     r2, r2, r0              /* r2 <- source end address */
  92 next2:
  93         ldmia   r0!, {r3 - r10}         /* copy from source address [r0] */
  94         stmia   r1!, {r3 - r10}         /* copy to   target address [r1] */
  95         cmp     r0, r2                  /* until source end address [r2] */
  96         bne     next2
  97         mov     pc, lr                  /* back to caller */
  98
  99 /* ***************************************************************************
 100  *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
 101  *               -executed from SRAM.
 102  *  R0 = CM_CLKEN_PLL-bypass value
 103  *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
 104  *  R2 = CM_CLKSEL_CORE-divider values
 105  *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
 106  *
 107  *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
 108  *        confused.  A reset of the controller gets it back.  Taking away its
 109  *        L3 when its not in self refresh seems bad for it.  Normally, this
 110  *        code runs from flash before SDR is init so that should be ok.
 111  ****************************************************************************/
 112 .global go_to_speed
 113  go_to_speed:
 114         stmfd sp!, {r4 - r6}
 115
 116         /* move into fast relock bypass */
 117         ldr     r4, pll_ctl_add
 118         str     r0, [r4]
 119 wait1:
 120         ldr     r5, [r3]                /* get status */
 121         and     r5, r5, #0x1            /* isolate core status */
 122         cmp     r5, #0x1                /* still locked? */
 123         beq     wait1                   /* if lock, loop */
 124
 125         /* set new dpll dividers _after_ in bypass */
 126         ldr     r5, pll_div_add1
 127         str     r1, [r5]                /* set m, n, m2 */
 128         ldr     r5, pll_div_add2
 129         str     r2, [r5]                /* set l3/l4/.. dividers*/
 130         ldr     r5, pll_div_add3        /* wkup */
 131         ldr     r2, pll_div_val3        /* rsm val */
 132         str     r2, [r5]
 133         ldr     r5, pll_div_add4        /* gfx */
 134         ldr     r2, pll_div_val4
 135         str     r2, [r5]
 136         ldr     r5, pll_div_add5        /* emu */
 137         ldr     r2, pll_div_val5
 138         str     r2, [r5]
 139
 140         /* now prepare GPMC (flash) for new dpll speed */
 141         /* flash needs to be stable when we jump back to it */
 142         ldr     r5, flash_cfg3_addr
 143         ldr     r2, flash_cfg3_val
 144         str     r2, [r5]
 145         ldr     r5, flash_cfg4_addr
 146         ldr     r2, flash_cfg4_val
 147         str     r2, [r5]
 148         ldr     r5, flash_cfg5_addr
 149         ldr     r2, flash_cfg5_val
 150         str     r2, [r5]
 151         ldr     r5, flash_cfg1_addr
 152         ldr     r2, [r5]
 153         orr     r2, r2, #0x3            /* up gpmc divider */
 154         str     r2, [r5]
 155
 156         /* lock DPLL3 and wait a bit */
 157         orr     r0, r0, #0x7    /* set up for lock mode */
 158         str     r0, [r4]        /* lock */
 159         nop                     /* ARM slow at this point working at sys_clk */
 160         nop
 161         nop
 162         nop
 163 wait2:
 164         ldr     r5, [r3]        /* get status */
 165         and     r5, r5, #0x1    /* isolate core status */
 166         cmp     r5, #0x1        /* still locked? */
 167         bne     wait2           /* if lock, loop */
 168         nop
 169         nop
 170         nop
 171         nop
 172         ldmfd   sp!, {r4 - r6}
 173         mov     pc, lr          /* back to caller, locked */
 174
 175 _go_to_speed: .word go_to_speed
 176
 177 /* these constants need to be close for PIC code */
 178 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
 179 flash_cfg1_addr:
 180         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
 181 flash_cfg3_addr:
 182         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
 183 flash_cfg3_val:
 184         .word STNOR_GPMC_CONFIG3
 185 flash_cfg4_addr:
 186         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
 187 flash_cfg4_val:
 188         .word STNOR_GPMC_CONFIG4
 189 flash_cfg5_val:
 190         .word STNOR_GPMC_CONFIG5
 191 flash_cfg5_addr:
 192         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
 193 pll_ctl_add:
 194         .word CM_CLKEN_PLL
 195 pll_div_add1:
 196         .word CM_CLKSEL1_PLL
 197 pll_div_add2:
 198         .word CM_CLKSEL_CORE
 199 pll_div_add3:
 200         .word CM_CLKSEL_WKUP
 201 pll_div_val3:
 202         .word (WKUP_RSM << 1)
 203 pll_div_add4:
 204         .word CM_CLKSEL_GFX
 205 pll_div_val4:
 206         .word (GFX_DIV << 0)
 207 pll_div_add5:
 208         .word CM_CLKSEL1_EMU
 209 pll_div_val5:
 210         .word CLSEL1_EMU_VAL
 211
 212 #endif
 213
 214 .globl lowlevel_init
 215 lowlevel_init:
 216         ldr     sp, SRAM_STACK
 217         str     ip, [sp]        /* stash old link register */
 218         mov     ip, lr          /* save link reg across call */
 219         bl      s_init          /* go setup pll, mux, memory */
 220         ldr     ip, [sp]        /* restore save ip */
 221         mov     lr, ip          /* restore link reg */
 222
 223         /* back to arch calling code */
 224         mov     pc, lr
 225
 226         /* the literal pools origin */
 227         .ltorg
 228
 229 REG_CONTROL_STATUS:
 230         .word CONTROL_STATUS
 231 SRAM_STACK:
 232         .word LOW_LEVEL_SRAM_STACK
 233
 234 /* DPLL(1-4) PARAM TABLES */
 235
 236 /*
 237  * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
 238  * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
 239  * The values are defined for all possible sysclk and for ES1 and ES2.
 240  */
 241
 242 mpu_dpll_param:
 243 /* 12MHz */
 244 /* ES1 */
 245 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
 246 /* ES2 */
 247 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
 248 /* 3410 */
 249 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
 250
 251 /* 13MHz */
 252 /* ES1 */
 253 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
 254 /* ES2 */
 255 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
 256 /* 3410 */
 257 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
 258
 259 /* 19.2MHz */
 260 /* ES1 */
 261 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
 262 /* ES2 */
 263 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
 264 /* 3410 */
 265 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
 266
 267 /* 26MHz */
 268 /* ES1 */
 269 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
 270 /* ES2 */
 271 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
 272 /* 3410 */
 273 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
 274
 275 /* 38.4MHz */
 276 /* ES1 */
 277 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
 278 /* ES2 */
 279 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
 280 /* 3410 */
 281 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
 282
 283
 284 .globl get_mpu_dpll_param
 285 get_mpu_dpll_param:
 286         adr     r0, mpu_dpll_param
 287         mov     pc, lr
 288
 289 iva_dpll_param:
 290 /* 12MHz */
 291 /* ES1 */
 292 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
 293 /* ES2 */
 294 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
 295 /* 3410 */
 296 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
 297
 298 /* 13MHz */
 299 /* ES1 */
 300 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
 301 /* ES2 */
 302 .word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
 303 /* 3410 */
 304 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
 305
 306 /* 19.2MHz */
 307 /* ES1 */
 308 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
 309 /* ES2 */
 310 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
 311 /* 3410 */
 312 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
 313
 314 /* 26MHz */
 315 /* ES1 */
 316 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
 317 /* ES2 */
 318 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
 319 /* 3410 */
 320 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
 321
 322 /* 38.4MHz */
 323 /* ES1 */
 324 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
 325 /* ES2 */
 326 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
 327 /* 3410 */
 328 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
 329
 330
 331 .globl get_iva_dpll_param
 332 get_iva_dpll_param:
 333         adr     r0, iva_dpll_param
 334         mov     pc, lr
 335
 336 /* Core DPLL targets for L3 at 166 & L133 */
 337 core_dpll_param:
 338 /* 12MHz */
 339 /* ES1 */
 340 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
 341 /* ES2 */
 342 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 343 /* 3410 */
 344 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 345
 346 /* 13MHz */
 347 /* ES1 */
 348 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
 349 /* ES2 */
 350 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 351 /* 3410 */
 352 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 353
 354 /* 19.2MHz */
 355 /* ES1 */
 356 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
 357 /* ES2 */
 358 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 359 /* 3410 */
 360 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 361
 362 /* 26MHz */
 363 /* ES1 */
 364 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
 365 /* ES2 */
 366 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 367 /* 3410 */
 368 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 369
 370 /* 38.4MHz */
 371 /* ES1 */
 372 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
 373 /* ES2 */
 374 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 375 /* 3410 */
 376 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 377
 378 .globl get_core_dpll_param
 379 get_core_dpll_param:
 380         adr     r0, core_dpll_param
 381         mov     pc, lr
 382
 383 /* PER DPLL values are same for both ES1 and ES2 */
 384 per_dpll_param:
 385 /* 12MHz */
 386 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
 387
 388 /* 13MHz */
 389 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
 390
 391 /* 19.2MHz */
 392 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
 393
 394 /* 26MHz */
 395 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
 396
 397 /* 38.4MHz */
 398 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
 399
 400 .globl get_per_dpll_param
 401 get_per_dpll_param:
 402         adr     r0, per_dpll_param
 403         mov     pc, lr
 404
 405 /* PER2 DPLL values */
 406 per2_dpll_param:
 407 /* 12MHz */
 408 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
 409
 410 /* 13MHz */
 411 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
 412
 413 /* 19.2MHz */
 414 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
 415
 416 /* 26MHz */
 417 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
 418
 419 /* 38.4MHz */
 420 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
 421
 422 .globl get_per2_dpll_param
 423 get_per2_dpll_param:
 424         adr     r0, per2_dpll_param
 425         mov     pc, lr
 426
 427 /*
 428  * Tables for 36XX/37XX devices
 429  *
 430  */
 431 mpu_36x_dpll_param:
 432 /* 12MHz */
 433 .word 50, 0, 0, 1
 434 /* 13MHz */
 435 .word 600, 12, 0, 1
 436 /* 19.2MHz */
 437 .word 125, 3, 0, 1
 438 /* 26MHz */
 439 .word 300, 12, 0, 1
 440 /* 38.4MHz */
 441 .word 125, 7, 0, 1
 442
 443 iva_36x_dpll_param:
 444 /* 12MHz */
 445 .word 130, 2, 0, 1
 446 /* 13MHz */
 447 .word 20, 0, 0, 1
 448 /* 19.2MHz */
 449 .word 325, 11, 0, 1
 450 /* 26MHz */
 451 .word 10, 0, 0, 1
 452 /* 38.4MHz */
 453 .word 325, 23, 0, 1
 454
 455 core_36x_dpll_param:
 456 /* 12MHz */
 457 .word 100, 2, 0, 1
 458 /* 13MHz */
 459 .word 400, 12, 0, 1
 460 /* 19.2MHz */
 461 .word 375, 17, 0, 1
 462 /* 26MHz */
 463 .word 200, 12, 0, 1
 464 /* 38.4MHz */
 465 .word 375, 35, 0, 1
 466
 467 per_36x_dpll_param:
 468 /*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
 469 .word 12000,    360,    4,     9,      16,     5,     4,      3,      1
 470 .word 13000,    864,   12,     9,      16,     9,     4,      3,      1
 471 .word 19200,    360,    7,     9,      16,     5,     4,      3,      1
 472 .word 26000,    432,   12,     9,      16,     9,     4,      3,      1
 473 .word 38400,    360,   15,     9,      16,     5,     4,      3,      1
 474
 475 .globl get_36x_mpu_dpll_param
 476 get_36x_mpu_dpll_param:
 477         adr     r0, mpu_36x_dpll_param
 478         mov     pc, lr
 479
 480 .globl get_36x_iva_dpll_param
 481 get_36x_iva_dpll_param:
 482         adr     r0, iva_36x_dpll_param
 483         mov     pc, lr
 484
 485 .globl get_36x_core_dpll_param
 486 get_36x_core_dpll_param:
 487         adr     r0, core_36x_dpll_param
 488         mov     pc, lr
 489
 490 .globl get_36x_per_dpll_param
 491 get_36x_per_dpll_param:
 492         adr     r0, per_36x_dpll_param
 493         mov     pc, lr