arch/arm/cpu/armv7/omap4/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP4
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 #include <common.h>
  29 #include <asm/arch/omap.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/omap_common.h>
  32 #include <asm/arch/clocks.h>
  33 #include <asm/omap_gpio.h>
  34 #include <asm/io.h>
  35
  36 struct prcm_regs const **prcm =
  37                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  38 struct dplls const **dplls_data =
  39                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  40 struct vcores_data const **omap_vcores =
  41                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  42 struct omap_sys_ctrl_regs const **ctrl =
  43         (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
  44
  45 /*
  46  * The M & N values in the following tables are created using the
  47  * following tool:
  48  * tools/omap/clocks_get_m_n.c
  49  * Please use this tool for creating the table for any new frequency.
  50  */
  51
  52 /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
  53 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
  54         {175, 2, 1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  55         {700, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  56         {125, 2, 1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  57         {401, 10, 1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  58         {350, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  59         {700, 26, 1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  60         {638, 34, 1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  61 };
  62
  63 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
  64 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  65         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  66         {800, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  67         {619, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
  68         {125, 2, 1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  69         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  70         {800, 26, 1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  71         {125, 5, 1, -1, -1, -1, -1, -1, -1, -1}         /* 38.4 MHz */
  72 };
  73
  74 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
  75 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
  76         {50, 0, 1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  77         {600, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  78         {250, 6, 1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  79         {125, 3, 1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  80         {300, 12, 1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  81         {200, 8, 1, -1, -1, -1, -1, -1, -1, -1},        /* 27 MHz   */
  82         {125, 7, 1, -1, -1, -1, -1, -1, -1, -1}         /* 38.4 MHz */
  83 };
  84
  85 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  86         {200, 2, 1, 5, 8, 4, 6, 5, -1, -1},     /* 12 MHz   */
  87         {800, 12, 1, 5, 8, 4, 6, 5, -1, -1},    /* 13 MHz   */
  88         {619, 12, 1, 5, 8, 4, 6, 5, -1, -1},    /* 16.8 MHz */
  89         {125, 2, 1, 5, 8, 4, 6, 5, -1, -1},     /* 19.2 MHz */
  90         {400, 12, 1, 5, 8, 4, 6, 5, -1, -1},    /* 26 MHz   */
  91         {800, 26, 1, 5, 8, 4, 6, 5, -1, -1},    /* 27 MHz   */
  92         {125, 5, 1, 5, 8, 4, 6, 5, -1, -1}      /* 38.4 MHz */
  93 };
  94
  95 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
  96         {127, 1, 1, 5, 8, 4, 6, 5, -1, -1},     /* 12 MHz   */
  97         {762, 12, 1, 5, 8, 4, 6, 5, -1, -1},    /* 13 MHz   */
  98         {635, 13, 1, 5, 8, 4, 6, 5, -1, -1},    /* 16.8 MHz */
  99         {635, 15, 1, 5, 8, 4, 6, 5, -1, -1},    /* 19.2 MHz */
 100         {381, 12, 1, 5, 8, 4, 6, 5, -1, -1},    /* 26 MHz   */
 101         {254, 8, 1, 5, 8, 4, 6, 5, -1, -1},     /* 27 MHz   */
 102         {496, 24, 1, 5, 8, 4, 6, 5, -1, -1}     /* 38.4 MHz */
 103 };
 104
 105 static const struct dpll_params
 106                 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
 107         {200, 2, 2, 5, 8, 4, 6, 5, -1, -1},     /* 12 MHz   */
 108         {800, 12, 2, 5, 8, 4, 6, 5, -1, -1},    /* 13 MHz   */
 109         {619, 12, 2, 5, 8, 4, 6, 5, -1, -1},    /* 16.8 MHz */
 110         {125, 2, 2, 5, 8, 4, 6, 5, -1, -1},     /* 19.2 MHz */
 111         {400, 12, 2, 5, 8, 4, 6, 5, -1, -1},    /* 26 MHz   */
 112         {800, 26, 2, 5, 8, 4, 6, 5, -1, -1},    /* 27 MHz   */
 113         {125, 5, 2, 5, 8, 4, 6, 5, -1, -1}      /* 38.4 MHz */
 114 };
 115
 116 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
 117         {64, 0, 8, 6, 12, 9, 4, 5, -1, -1},     /* 12 MHz   */
 118         {768, 12, 8, 6, 12, 9, 4, 5, -1, -1},   /* 13 MHz   */
 119         {320, 6, 8, 6, 12, 9, 4, 5, -1, -1},    /* 16.8 MHz */
 120         {40, 0, 8, 6, 12, 9, 4, 5, -1, -1},     /* 19.2 MHz */
 121         {384, 12, 8, 6, 12, 9, 4, 5, -1, -1},   /* 26 MHz   */
 122         {256, 8, 8, 6, 12, 9, 4, 5, -1, -1},    /* 27 MHz   */
 123         {20, 0, 8, 6, 12, 9, 4, 5, -1, -1}      /* 38.4 MHz */
 124 };
 125
 126 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
 127         {931, 11, -1, -1, 4, 7, -1, -1, -1, -1},        /* 12 MHz   */
 128         {931, 12, -1, -1, 4, 7, -1, -1, -1, -1},        /* 13 MHz   */
 129         {665, 11, -1, -1, 4, 7, -1, -1, -1, -1},        /* 16.8 MHz */
 130         {727, 14, -1, -1, 4, 7, -1, -1, -1, -1},        /* 19.2 MHz */
 131         {931, 25, -1, -1, 4, 7, -1, -1, -1, -1},        /* 26 MHz   */
 132         {931, 26, -1, -1, 4, 7, -1, -1, -1, -1},        /* 27 MHz   */
 133         {291, 11, -1, -1, 4, 7, -1, -1, -1, -1}         /* 38.4 MHz */
 134 };
 135
 136 /* ABE M & N values with sys_clk as source */
 137 static const struct dpll_params
 138                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 139         {49, 5, 1, 1, -1, -1, -1, -1, -1, -1},  /* 12 MHz   */
 140         {68, 8, 1, 1, -1, -1, -1, -1, -1, -1},  /* 13 MHz   */
 141         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1},  /* 16.8 MHz */
 142         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1},  /* 19.2 MHz */
 143         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1},  /* 26 MHz   */
 144         {29, 7, 1, 1, -1, -1, -1, -1, -1, -1},  /* 27 MHz   */
 145         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1}  /* 38.4 MHz */
 146 };
 147
 148 /* ABE M & N values with 32K clock as source */
 149 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 150         750, 0, 1, 1, -1, -1, -1, -1, -1, -1
 151 };
 152
 153 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 154         {80, 0, 2, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 155         {960, 12, 2, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 156         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 157         {50, 0, 2, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 158         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 159         {320, 8, 2, -1, -1, -1, -1, -1, -1, -1},        /* 27 MHz   */
 160         {25, 0, 2, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 161 };
 162
 163 struct dplls omap4430_dplls_es1 = {
 164         .mpu = mpu_dpll_params_1200mhz,
 165         .core = core_dpll_params_es1_1524mhz,
 166         .per = per_dpll_params_1536mhz,
 167         .iva = iva_dpll_params_1862mhz,
 168 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 169         .abe = abe_dpll_params_sysclk_196608khz,
 170 #else
 171         .abe = &abe_dpll_params_32k_196608khz,
 172 #endif
 173         .usb = usb_dpll_params_1920mhz
 174 };
 175
 176 struct dplls omap4430_dplls = {
 177         .mpu = mpu_dpll_params_1600mhz,
 178         .core = core_dpll_params_es2_1600mhz_ddr200mhz,
 179         .per = per_dpll_params_1536mhz,
 180         .iva = iva_dpll_params_1862mhz,
 181 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 182         .abe = abe_dpll_params_sysclk_196608khz,
 183 #else
 184         .abe = &abe_dpll_params_32k_196608khz,
 185 #endif
 186         .usb = usb_dpll_params_1920mhz
 187 };
 188
 189 struct dplls omap4460_dplls = {
 190         .mpu = mpu_dpll_params_1400mhz,
 191         .core = core_dpll_params_1600mhz,
 192         .per = per_dpll_params_1536mhz,
 193         .iva = iva_dpll_params_1862mhz,
 194 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 195         .abe = abe_dpll_params_sysclk_196608khz,
 196 #else
 197         .abe = &abe_dpll_params_32k_196608khz,
 198 #endif
 199         .usb = usb_dpll_params_1920mhz
 200 };
 201
 202 struct pmic_data twl6030_4430es1 = {
 203         .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
 204         .step = 12660, /* 10 mV represented in uV */
 205         /* The code starts at 1 not 0 */
 206         .start_code = 1,
 207 };
 208
 209 struct pmic_data twl6030 = {
 210         .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
 211         .step = 12660, /* 10 mV represented in uV */
 212         /* The code starts at 1 not 0 */
 213         .start_code = 1,
 214 };
 215
 216 struct pmic_data tps62361 = {
 217         .base_offset = TPS62361_BASE_VOLT_MV,
 218         .step = 10000, /* 10 mV represented in uV */
 219         .start_code = 0,
 220         .gpio = TPS62361_VSEL0_GPIO,
 221         .gpio_en = 1
 222 };
 223
 224 struct vcores_data omap4430_volts_es1 = {
 225         .mpu.value = 1325,
 226         .mpu.addr = SMPS_REG_ADDR_VCORE1,
 227         .mpu.pmic = &twl6030_4430es1,
 228
 229         .core.value = 1200,
 230         .core.addr = SMPS_REG_ADDR_VCORE3,
 231         .core.pmic = &twl6030_4430es1,
 232
 233         .mm.value = 1200,
 234         .mm.addr = SMPS_REG_ADDR_VCORE2,
 235         .mm.pmic = &twl6030_4430es1,
 236 };
 237
 238 struct vcores_data omap4430_volts = {
 239         .mpu.value = 1325,
 240         .mpu.addr = SMPS_REG_ADDR_VCORE1,
 241         .mpu.pmic = &twl6030,
 242
 243         .core.value = 1200,
 244         .core.addr = SMPS_REG_ADDR_VCORE3,
 245         .core.pmic = &twl6030,
 246
 247         .mm.value = 1200,
 248         .mm.addr = SMPS_REG_ADDR_VCORE2,
 249         .mm.pmic = &twl6030,
 250 };
 251
 252 struct vcores_data omap4460_volts = {
 253         .mpu.value = 1203,
 254         .mpu.addr = TPS62361_REG_ADDR_SET1,
 255         .mpu.pmic = &tps62361,
 256
 257         .core.value = 1200,
 258         .core.addr = SMPS_REG_ADDR_VCORE1,
 259         .core.pmic = &tps62361,
 260
 261         .mm.value = 1200,
 262         .mm.addr = SMPS_REG_ADDR_VCORE2,
 263         .mm.pmic = &tps62361,
 264 };
 265
 266 /*
 267  * Enable essential clock domains, modules and
 268  * do some additional special settings needed
 269  */
 270 void enable_basic_clocks(void)
 271 {
 272         u32 const clk_domains_essential[] = {
 273                 (*prcm)->cm_l4per_clkstctrl,
 274                 (*prcm)->cm_l3init_clkstctrl,
 275                 (*prcm)->cm_memif_clkstctrl,
 276                 (*prcm)->cm_l4cfg_clkstctrl,
 277                 0
 278         };
 279
 280         u32 const clk_modules_hw_auto_essential[] = {
 281                 (*prcm)->cm_l3_2_gpmc_clkctrl,
 282                 (*prcm)->cm_memif_emif_1_clkctrl,
 283                 (*prcm)->cm_memif_emif_2_clkctrl,
 284                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 285                 (*prcm)->cm_wkup_gpio1_clkctrl,
 286                 (*prcm)->cm_l4per_gpio2_clkctrl,
 287                 (*prcm)->cm_l4per_gpio3_clkctrl,
 288                 (*prcm)->cm_l4per_gpio4_clkctrl,
 289                 (*prcm)->cm_l4per_gpio5_clkctrl,
 290                 (*prcm)->cm_l4per_gpio6_clkctrl,
 291                 0
 292         };
 293
 294         u32 const clk_modules_explicit_en_essential[] = {
 295                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 296                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 297                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 298                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 299                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 300                 (*prcm)->cm_l4per_uart3_clkctrl,
 301                 0
 302         };
 303
 304         /* Enable optional additional functional clock for GPIO4 */
 305         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 306                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 307
 308         /* Enable 96 MHz clock for MMC1 & MMC2 */
 309         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 310                         HSMMC_CLKCTRL_CLKSEL_MASK);
 311         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 312                         HSMMC_CLKCTRL_CLKSEL_MASK);
 313
 314         /* Select 32KHz clock as the source of GPTIMER1 */
 315         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 316                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 317
 318         /* Enable optional 48M functional clock for USB  PHY */
 319         setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
 320                         USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
 321
 322         do_enable_clocks(clk_domains_essential,
 323                          clk_modules_hw_auto_essential,
 324                          clk_modules_explicit_en_essential,
 325                          1);
 326 }
 327
 328 void enable_basic_uboot_clocks(void)
 329 {
 330         u32 const clk_domains_essential[] = {
 331                 0
 332         };
 333
 334         u32 const clk_modules_hw_auto_essential[] = {
 335                 (*prcm)->cm_l3init_hsusbotg_clkctrl,
 336                 (*prcm)->cm_l3init_usbphy_clkctrl,
 337                 (*prcm)->cm_l3init_usbphy_clkctrl,
 338                 (*prcm)->cm_clksel_usb_60mhz,
 339                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 340                 0
 341         };
 342
 343         u32 const clk_modules_explicit_en_essential[] = {
 344                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 345                 (*prcm)->cm_l4per_i2c1_clkctrl,
 346                 (*prcm)->cm_l4per_i2c2_clkctrl,
 347                 (*prcm)->cm_l4per_i2c3_clkctrl,
 348                 (*prcm)->cm_l4per_i2c4_clkctrl,
 349                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 350                 0
 351         };
 352
 353         do_enable_clocks(clk_domains_essential,
 354                          clk_modules_hw_auto_essential,
 355                          clk_modules_explicit_en_essential,
 356                          1);
 357 }
 358
 359 /*
 360  * Enable non-essential clock domains, modules and
 361  * do some additional special settings needed
 362  */
 363 void enable_non_essential_clocks(void)
 364 {
 365         u32 const clk_domains_non_essential[] = {
 366                 (*prcm)->cm_mpu_m3_clkstctrl,
 367                 (*prcm)->cm_ivahd_clkstctrl,
 368                 (*prcm)->cm_dsp_clkstctrl,
 369                 (*prcm)->cm_dss_clkstctrl,
 370                 (*prcm)->cm_sgx_clkstctrl,
 371                 (*prcm)->cm1_abe_clkstctrl,
 372                 (*prcm)->cm_c2c_clkstctrl,
 373                 (*prcm)->cm_cam_clkstctrl,
 374                 (*prcm)->cm_dss_clkstctrl,
 375                 (*prcm)->cm_sdma_clkstctrl,
 376                 0
 377         };
 378
 379         u32 const clk_modules_hw_auto_non_essential[] = {
 380                 (*prcm)->cm_l3instr_l3_3_clkctrl,
 381                 (*prcm)->cm_l3instr_l3_instr_clkctrl,
 382                 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
 383                 (*prcm)->cm_l3init_hsi_clkctrl,
 384                 0
 385         };
 386
 387         u32 const clk_modules_explicit_en_non_essential[] = {
 388                 (*prcm)->cm1_abe_aess_clkctrl,
 389                 (*prcm)->cm1_abe_pdm_clkctrl,
 390                 (*prcm)->cm1_abe_dmic_clkctrl,
 391                 (*prcm)->cm1_abe_mcasp_clkctrl,
 392                 (*prcm)->cm1_abe_mcbsp1_clkctrl,
 393                 (*prcm)->cm1_abe_mcbsp2_clkctrl,
 394                 (*prcm)->cm1_abe_mcbsp3_clkctrl,
 395                 (*prcm)->cm1_abe_slimbus_clkctrl,
 396                 (*prcm)->cm1_abe_timer5_clkctrl,
 397                 (*prcm)->cm1_abe_timer6_clkctrl,
 398                 (*prcm)->cm1_abe_timer7_clkctrl,
 399                 (*prcm)->cm1_abe_timer8_clkctrl,
 400                 (*prcm)->cm1_abe_wdt3_clkctrl,
 401                 (*prcm)->cm_l4per_gptimer9_clkctrl,
 402                 (*prcm)->cm_l4per_gptimer10_clkctrl,
 403                 (*prcm)->cm_l4per_gptimer11_clkctrl,
 404                 (*prcm)->cm_l4per_gptimer3_clkctrl,
 405                 (*prcm)->cm_l4per_gptimer4_clkctrl,
 406                 (*prcm)->cm_l4per_hdq1w_clkctrl,
 407                 (*prcm)->cm_l4per_mcbsp4_clkctrl,
 408                 (*prcm)->cm_l4per_mcspi2_clkctrl,
 409                 (*prcm)->cm_l4per_mcspi3_clkctrl,
 410                 (*prcm)->cm_l4per_mcspi4_clkctrl,
 411                 (*prcm)->cm_l4per_mmcsd3_clkctrl,
 412                 (*prcm)->cm_l4per_mmcsd4_clkctrl,
 413                 (*prcm)->cm_l4per_mmcsd5_clkctrl,
 414                 (*prcm)->cm_l4per_uart1_clkctrl,
 415                 (*prcm)->cm_l4per_uart2_clkctrl,
 416                 (*prcm)->cm_l4per_uart4_clkctrl,
 417                 (*prcm)->cm_wkup_keyboard_clkctrl,
 418                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 419                 (*prcm)->cm_cam_iss_clkctrl,
 420                 (*prcm)->cm_cam_fdif_clkctrl,
 421                 (*prcm)->cm_dss_dss_clkctrl,
 422                 (*prcm)->cm_sgx_sgx_clkctrl,
 423                 0
 424         };
 425
 426         /* Enable optional functional clock for ISS */
 427         setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 428
 429         /* Enable all optional functional clocks of DSS */
 430         setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 431
 432         do_enable_clocks(clk_domains_non_essential,
 433                          clk_modules_hw_auto_non_essential,
 434                          clk_modules_explicit_en_non_essential,
 435                          0);
 436
 437         /* Put camera module in no sleep mode */
 438         clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
 439                         MODULE_CLKCTRL_MODULEMODE_MASK,
 440                         CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 441                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 442 }
 443
 444 void hw_data_init(void)
 445 {
 446         u32 omap_rev = omap_revision();
 447
 448         (*prcm) = &omap4_prcm;
 449
 450         switch (omap_rev) {
 451
 452         case OMAP4430_ES1_0:
 453         *dplls_data = &omap4430_dplls_es1;
 454         *omap_vcores = &omap4430_volts_es1;
 455         break;
 456
 457         case OMAP4430_ES2_0:
 458         case OMAP4430_ES2_1:
 459         case OMAP4430_ES2_2:
 460         case OMAP4430_ES2_3:
 461         *dplls_data = &omap4430_dplls;
 462         *omap_vcores = &omap4430_volts;
 463         break;
 464
 465         case OMAP4460_ES1_0:
 466         case OMAP4460_ES1_1:
 467         *dplls_data = &omap4460_dplls;
 468         *omap_vcores = &omap4460_volts;
 469         break;
 470
 471         default:
 472                 printf("\n INVALID OMAP REVISION ");
 473         }
 474
 475         *ctrl = &omap4_ctrl;
 476 }