3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
33 #include <asm/omap_gpio.h>
37 struct prcm_regs
const **prcm
=
38 (struct prcm_regs
const **) OMAP_SRAM_SCRATCH_PRCM_PTR
;
39 struct dplls
const **dplls_data
=
40 (struct dplls
const **) OMAP_SRAM_SCRATCH_DPLLS_PTR
;
41 struct vcores_data
const **omap_vcores
=
42 (struct vcores_data
const **) OMAP_SRAM_SCRATCH_VCORES_PTR
;
43 struct omap_sys_ctrl_regs
const **ctrl
=
44 (struct omap_sys_ctrl_regs
const **)OMAP5_SRAM_SCRATCH_SYS_CTRL
;
46 /* OPP HIGH FREQUENCY for ES2.0 */
47 static const struct dpll_params mpu_dpll_params_1_5ghz
[NUM_SYS_CLKS
] = {
48 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
50 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
51 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
52 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
53 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
54 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
57 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
58 static const struct dpll_params mpu_dpll_params_1100mhz
[NUM_SYS_CLKS
] = {
59 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
61 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
62 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
63 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
64 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
65 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
68 /* OPP NOM FREQUENCY for ES1.0 */
69 static const struct dpll_params mpu_dpll_params_800mhz
[NUM_SYS_CLKS
] = {
70 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
72 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
73 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
74 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
75 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
76 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
79 /* OPP LOW FREQUENCY for ES1.0 */
80 static const struct dpll_params mpu_dpll_params_400mhz
[NUM_SYS_CLKS
] = {
81 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
83 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
84 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
85 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
86 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
87 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
90 /* OPP LOW FREQUENCY for ES2.0 */
91 static const struct dpll_params mpu_dpll_params_499mhz
[NUM_SYS_CLKS
] = {
92 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
94 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
95 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
96 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
97 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
98 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
101 static const struct dpll_params
102 core_dpll_params_2128mhz_ddr532
[NUM_SYS_CLKS
] = {
103 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
105 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
106 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
107 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
112 static const struct dpll_params
113 core_dpll_params_2128mhz_ddr532_es2
[NUM_SYS_CLKS
] = {
114 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
116 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
117 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
118 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
119 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
120 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
123 static const struct dpll_params
124 core_dpll_params_2128mhz_ddr266
[NUM_SYS_CLKS
] = {
125 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
128 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
129 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
130 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
134 static const struct dpll_params
135 core_dpll_params_2128mhz_ddr266_es2
[NUM_SYS_CLKS
] = {
136 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
138 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
139 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
140 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
142 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
145 static const struct dpll_params per_dpll_params_768mhz
[NUM_SYS_CLKS
] = {
146 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
148 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
149 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
150 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
151 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
152 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
155 static const struct dpll_params per_dpll_params_768mhz_es2
[NUM_SYS_CLKS
] = {
156 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
158 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
159 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
160 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
161 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
162 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
165 static const struct dpll_params iva_dpll_params_2330mhz
[NUM_SYS_CLKS
] = {
166 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
168 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
169 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
170 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
171 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
172 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
175 /* ABE M & N values with sys_clk as source */
176 static const struct dpll_params
177 abe_dpll_params_sysclk_196608khz
[NUM_SYS_CLKS
] = {
178 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
179 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
180 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
181 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
182 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
183 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
184 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
187 /* ABE M & N values with 32K clock as source */
188 static const struct dpll_params abe_dpll_params_32k_196608khz
= {
189 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
192 static const struct dpll_params usb_dpll_params_1920mhz
[NUM_SYS_CLKS
] = {
193 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
194 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
195 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
196 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
197 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
198 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
199 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
202 struct dplls omap5_dplls_es1
= {
203 .mpu
= mpu_dpll_params_800mhz
,
204 .core
= core_dpll_params_2128mhz_ddr532
,
205 .per
= per_dpll_params_768mhz
,
206 .iva
= iva_dpll_params_2330mhz
,
207 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
208 .abe
= abe_dpll_params_sysclk_196608khz
,
210 .abe
= &abe_dpll_params_32k_196608khz
,
212 .usb
= usb_dpll_params_1920mhz
215 struct dplls omap5_dplls_es2
= {
216 .mpu
= mpu_dpll_params_1100mhz
,
217 .core
= core_dpll_params_2128mhz_ddr532_es2
,
218 .per
= per_dpll_params_768mhz_es2
,
219 .iva
= iva_dpll_params_2330mhz
,
220 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
221 .abe
= abe_dpll_params_sysclk_196608khz
,
223 .abe
= &abe_dpll_params_32k_196608khz
,
225 .usb
= usb_dpll_params_1920mhz
228 struct pmic_data palmas
= {
229 .base_offset
= PALMAS_SMPS_BASE_VOLT_UV
,
230 .step
= 10000, /* 10 mV represented in uV */
232 * Offset codes 1-6 all give the base voltage in Palmas
233 * Offset code 0 switches OFF the SMPS
238 struct vcores_data omap5430_volts
= {
239 .mpu
.value
= VDD_MPU
,
240 .mpu
.addr
= SMPS_REG_ADDR_12_MPU
,
243 .core
.value
= VDD_CORE
,
244 .core
.addr
= SMPS_REG_ADDR_8_CORE
,
245 .core
.pmic
= &palmas
,
248 .mm
.addr
= SMPS_REG_ADDR_45_IVA
,
252 struct vcores_data omap5430_volts_es2
= {
253 .mpu
.value
= VDD_MPU_ES2
,
254 .mpu
.addr
= SMPS_REG_ADDR_12_MPU
,
257 .core
.value
= VDD_CORE_ES2
,
258 .core
.addr
= SMPS_REG_ADDR_8_CORE
,
259 .core
.pmic
= &palmas
,
261 .mm
.value
= VDD_MM_ES2
,
262 .mm
.addr
= SMPS_REG_ADDR_45_IVA
,
267 * Enable essential clock domains, modules and
268 * do some additional special settings needed
270 void enable_basic_clocks(void)
272 u32
const clk_domains_essential
[] = {
273 (*prcm
)->cm_l4per_clkstctrl
,
274 (*prcm
)->cm_l3init_clkstctrl
,
275 (*prcm
)->cm_memif_clkstctrl
,
276 (*prcm
)->cm_l4cfg_clkstctrl
,
280 u32
const clk_modules_hw_auto_essential
[] = {
281 (*prcm
)->cm_l3_2_gpmc_clkctrl
,
282 (*prcm
)->cm_memif_emif_1_clkctrl
,
283 (*prcm
)->cm_memif_emif_2_clkctrl
,
284 (*prcm
)->cm_l4cfg_l4_cfg_clkctrl
,
285 (*prcm
)->cm_wkup_gpio1_clkctrl
,
286 (*prcm
)->cm_l4per_gpio2_clkctrl
,
287 (*prcm
)->cm_l4per_gpio3_clkctrl
,
288 (*prcm
)->cm_l4per_gpio4_clkctrl
,
289 (*prcm
)->cm_l4per_gpio5_clkctrl
,
290 (*prcm
)->cm_l4per_gpio6_clkctrl
,
294 u32
const clk_modules_explicit_en_essential
[] = {
295 (*prcm
)->cm_wkup_gptimer1_clkctrl
,
296 (*prcm
)->cm_l3init_hsmmc1_clkctrl
,
297 (*prcm
)->cm_l3init_hsmmc2_clkctrl
,
298 (*prcm
)->cm_l4per_gptimer2_clkctrl
,
299 (*prcm
)->cm_wkup_wdtimer2_clkctrl
,
300 (*prcm
)->cm_l4per_uart3_clkctrl
,
301 (*prcm
)->cm_l4per_i2c1_clkctrl
,
305 /* Enable optional additional functional clock for GPIO4 */
306 setbits_le32((*prcm
)->cm_l4per_gpio4_clkctrl
,
307 GPIO4_CLKCTRL_OPTFCLKEN_MASK
);
309 /* Enable 96 MHz clock for MMC1 & MMC2 */
310 setbits_le32((*prcm
)->cm_l3init_hsmmc1_clkctrl
,
311 HSMMC_CLKCTRL_CLKSEL_MASK
);
312 setbits_le32((*prcm
)->cm_l3init_hsmmc2_clkctrl
,
313 HSMMC_CLKCTRL_CLKSEL_MASK
);
315 /* Set the correct clock dividers for mmc */
316 setbits_le32((*prcm
)->cm_l3init_hsmmc1_clkctrl
,
317 HSMMC_CLKCTRL_CLKSEL_DIV_MASK
);
318 setbits_le32((*prcm
)->cm_l3init_hsmmc2_clkctrl
,
319 HSMMC_CLKCTRL_CLKSEL_DIV_MASK
);
321 /* Select 32KHz clock as the source of GPTIMER1 */
322 setbits_le32((*prcm
)->cm_wkup_gptimer1_clkctrl
,
323 GPTIMER1_CLKCTRL_CLKSEL_MASK
);
325 do_enable_clocks(clk_domains_essential
,
326 clk_modules_hw_auto_essential
,
327 clk_modules_explicit_en_essential
,
330 /* Select 384Mhz for GPU as its the POR for ES1.0 */
331 setbits_le32((*prcm
)->cm_sgx_sgx_clkctrl
,
332 CLKSEL_GPU_HYD_GCLK_MASK
);
333 setbits_le32((*prcm
)->cm_sgx_sgx_clkctrl
,
334 CLKSEL_GPU_CORE_GCLK_MASK
);
336 /* Enable SCRM OPT clocks for PER and CORE dpll */
337 setbits_le32((*prcm
)->cm_wkupaon_scrm_clkctrl
,
338 OPTFCLKEN_SCRM_PER_MASK
);
339 setbits_le32((*prcm
)->cm_wkupaon_scrm_clkctrl
,
340 OPTFCLKEN_SCRM_CORE_MASK
);
343 void enable_basic_uboot_clocks(void)
345 u32
const clk_domains_essential
[] = {
349 u32
const clk_modules_hw_auto_essential
[] = {
353 u32
const clk_modules_explicit_en_essential
[] = {
354 (*prcm
)->cm_l4per_mcspi1_clkctrl
,
355 (*prcm
)->cm_l4per_i2c2_clkctrl
,
356 (*prcm
)->cm_l4per_i2c3_clkctrl
,
357 (*prcm
)->cm_l4per_i2c4_clkctrl
,
358 (*prcm
)->cm_l3init_hsusbtll_clkctrl
,
359 (*prcm
)->cm_l3init_hsusbhost_clkctrl
,
360 (*prcm
)->cm_l3init_fsusb_clkctrl
,
364 do_enable_clocks(clk_domains_essential
,
365 clk_modules_hw_auto_essential
,
366 clk_modules_explicit_en_essential
,
371 * Enable non-essential clock domains, modules and
372 * do some additional special settings needed
374 void enable_non_essential_clocks(void)
376 u32
const clk_domains_non_essential
[] = {
377 (*prcm
)->cm_mpu_m3_clkstctrl
,
378 (*prcm
)->cm_ivahd_clkstctrl
,
379 (*prcm
)->cm_dsp_clkstctrl
,
380 (*prcm
)->cm_dss_clkstctrl
,
381 (*prcm
)->cm_sgx_clkstctrl
,
382 (*prcm
)->cm1_abe_clkstctrl
,
383 (*prcm
)->cm_c2c_clkstctrl
,
384 (*prcm
)->cm_cam_clkstctrl
,
385 (*prcm
)->cm_dss_clkstctrl
,
386 (*prcm
)->cm_sdma_clkstctrl
,
390 u32
const clk_modules_hw_auto_non_essential
[] = {
391 (*prcm
)->cm_mpu_m3_mpu_m3_clkctrl
,
392 (*prcm
)->cm_ivahd_ivahd_clkctrl
,
393 (*prcm
)->cm_ivahd_sl2_clkctrl
,
394 (*prcm
)->cm_dsp_dsp_clkctrl
,
395 (*prcm
)->cm_l3instr_l3_3_clkctrl
,
396 (*prcm
)->cm_l3instr_l3_instr_clkctrl
,
397 (*prcm
)->cm_l3instr_intrconn_wp1_clkctrl
,
398 (*prcm
)->cm_l3init_hsi_clkctrl
,
399 (*prcm
)->cm_l4per_hdq1w_clkctrl
,
403 u32
const clk_modules_explicit_en_non_essential
[] = {
404 (*prcm
)->cm1_abe_aess_clkctrl
,
405 (*prcm
)->cm1_abe_pdm_clkctrl
,
406 (*prcm
)->cm1_abe_dmic_clkctrl
,
407 (*prcm
)->cm1_abe_mcasp_clkctrl
,
408 (*prcm
)->cm1_abe_mcbsp1_clkctrl
,
409 (*prcm
)->cm1_abe_mcbsp2_clkctrl
,
410 (*prcm
)->cm1_abe_mcbsp3_clkctrl
,
411 (*prcm
)->cm1_abe_slimbus_clkctrl
,
412 (*prcm
)->cm1_abe_timer5_clkctrl
,
413 (*prcm
)->cm1_abe_timer6_clkctrl
,
414 (*prcm
)->cm1_abe_timer7_clkctrl
,
415 (*prcm
)->cm1_abe_timer8_clkctrl
,
416 (*prcm
)->cm1_abe_wdt3_clkctrl
,
417 (*prcm
)->cm_l4per_gptimer9_clkctrl
,
418 (*prcm
)->cm_l4per_gptimer10_clkctrl
,
419 (*prcm
)->cm_l4per_gptimer11_clkctrl
,
420 (*prcm
)->cm_l4per_gptimer3_clkctrl
,
421 (*prcm
)->cm_l4per_gptimer4_clkctrl
,
422 (*prcm
)->cm_l4per_mcspi2_clkctrl
,
423 (*prcm
)->cm_l4per_mcspi3_clkctrl
,
424 (*prcm
)->cm_l4per_mcspi4_clkctrl
,
425 (*prcm
)->cm_l4per_mmcsd3_clkctrl
,
426 (*prcm
)->cm_l4per_mmcsd4_clkctrl
,
427 (*prcm
)->cm_l4per_mmcsd5_clkctrl
,
428 (*prcm
)->cm_l4per_uart1_clkctrl
,
429 (*prcm
)->cm_l4per_uart2_clkctrl
,
430 (*prcm
)->cm_l4per_uart4_clkctrl
,
431 (*prcm
)->cm_wkup_keyboard_clkctrl
,
432 (*prcm
)->cm_wkup_wdtimer2_clkctrl
,
433 (*prcm
)->cm_cam_iss_clkctrl
,
434 (*prcm
)->cm_cam_fdif_clkctrl
,
435 (*prcm
)->cm_dss_dss_clkctrl
,
436 (*prcm
)->cm_sgx_sgx_clkctrl
,
440 /* Enable optional functional clock for ISS */
441 setbits_le32((*prcm
)->cm_cam_iss_clkctrl
, ISS_CLKCTRL_OPTFCLKEN_MASK
);
443 /* Enable all optional functional clocks of DSS */
444 setbits_le32((*prcm
)->cm_dss_dss_clkctrl
, DSS_CLKCTRL_OPTFCLKEN_MASK
);
446 do_enable_clocks(clk_domains_non_essential
,
447 clk_modules_hw_auto_non_essential
,
448 clk_modules_explicit_en_non_essential
,
451 /* Put camera module in no sleep mode */
452 clrsetbits_le32((*prcm
)->cm_cam_clkstctrl
,
453 MODULE_CLKCTRL_MODULEMODE_MASK
,
454 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP
<<
455 MODULE_CLKCTRL_MODULEMODE_SHIFT
);
458 const struct ctrl_ioregs ioregs_omap5430
= {
459 .ctrl_ddrch
= DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN
,
460 .ctrl_lpddr2ch
= DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN
,
461 .ctrl_ddrio_0
= DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL
,
462 .ctrl_ddrio_1
= DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL
,
463 .ctrl_ddrio_2
= DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL
,
466 const struct ctrl_ioregs ioregs_omap5432_es1
= {
467 .ctrl_ddrch
= DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL
,
468 .ctrl_lpddr2ch
= 0x0,
469 .ctrl_ddr3ch
= DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL
,
470 .ctrl_ddrio_0
= DDR_IO_0_VREF_CELLS_DDR3_VALUE
,
471 .ctrl_ddrio_1
= DDR_IO_1_VREF_CELLS_DDR3_VALUE
,
472 .ctrl_ddrio_2
= DDR_IO_2_VREF_CELLS_DDR3_VALUE
,
473 .ctrl_emif_sdram_config_ext
= SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES
,
476 void hw_data_init(void)
478 u32 omap_rev
= omap_revision();
484 *prcm
= &omap5_es1_prcm
;
485 *dplls_data
= &omap5_dplls_es1
;
486 *omap_vcores
= &omap5430_volts
;
491 *prcm
= &omap5_es2_prcm
;
492 *dplls_data
= &omap5_dplls_es2
;
493 *omap_vcores
= &omap5430_volts_es2
;
497 printf("\n INVALID OMAP REVISION ");
503 void get_ioregs(const struct ctrl_ioregs
**regs
)
505 u32 omap_rev
= omap_revision();
509 *regs
= &ioregs_omap5430
;
512 *regs
= &ioregs_omap5432_es1
;
516 printf("\n INVALID OMAP REVISION ");