arch/arm/cpu/armv7/omap5/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP5
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <palmas.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/omap_gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/emif.h>
  21
  22 struct prcm_regs const **prcm =
  23                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  24 struct dplls const **dplls_data =
  25                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  26 struct vcores_data const **omap_vcores =
  27                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  28 struct omap_sys_ctrl_regs const **ctrl =
  29         (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  30
  31 /* OPP HIGH FREQUENCY for ES2.0 */
  32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  33         {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  34         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  35         {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  36         {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  37         {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  38         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  39         {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  40 };
  41
  42 /* OPP NOM FREQUENCY for ES1.0 */
  43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  44         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  45         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  46         {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  47         {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  48         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  49         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  50         {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  51 };
  52
  53 /* OPP LOW FREQUENCY for ES1.0 */
  54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  55         {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  56         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  57         {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  58         {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  59         {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  60         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  61         {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  62 };
  63
  64 /* OPP LOW FREQUENCY for ES2.0 */
  65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  66         {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
  67         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  68         {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  69         {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  70         {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  71         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  72         {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  73 };
  74
  75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
  76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  77         {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  78         {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
  79         {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
  80         {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  81         {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
  82         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  83         {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
  84 };
  85
  86 static const struct dpll_params
  87                         core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  88         {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 12 MHz   */
  89         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  90         {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 16.8 MHz */
  91         {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 19.2 MHz */
  92         {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 26 MHz   */
  93         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  94         {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}               /* 38.4 MHz */
  95 };
  96
  97 static const struct dpll_params
  98                         core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
  99         {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 12 MHz   */
 100         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 101         {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 16.8 MHz */
 102         {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 19.2 MHz */
 103         {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 26 MHz   */
 104         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 105         {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}                /* 38.4 MHz */
 106 };
 107
 108 static const struct dpll_params
 109                 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
 110         {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
 111         {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
 112         {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
 113         {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
 114         {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
 115         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 116         {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 117 };
 118
 119 static const struct dpll_params
 120                         core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
 121         {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 12 MHz   */
 122         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 123         {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 16.8 MHz */
 124         {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 19.2 MHz */
 125         {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 26 MHz   */
 126         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 127         {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}            /* 38.4 MHz */
 128 };
 129
 130 static const struct dpll_params
 131                         core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
 132         {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 12 MHz   */
 133         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 134         {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 16.8 MHz */
 135         {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 19.2 MHz */
 136         {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 26 MHz   */
 137         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 138         {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}             /* 38.4 MHz */
 139 };
 140
 141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 142         {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 143         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 144         {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 145         {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 146         {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 147         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 148         {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 149 };
 150
 151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 152         {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 153         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 154         {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 155         {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 156         {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 157         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 158         {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 159 };
 160
 161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 162         {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 12 MHz   */
 163         {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */
 164         {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},             /* 16.8 MHz */
 165         {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 19.2 MHz */
 166         {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},            /* 26 MHz   */
 167         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 168         {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 38.4 MHz */
 169 };
 170
 171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 172         {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 173         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 174         {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 175         {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 176         {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 177         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 178         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 179 };
 180
 181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 182         {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 183         {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
 184         {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 185         {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 186         {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 187         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 188         {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
 189 };
 190
 191 /* ABE M & N values with sys_clk as source */
 192 static const struct dpll_params
 193                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 194         {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 195         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 196         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 197         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 198         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 26 MHz   */
 199         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 200         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 201 };
 202
 203 /* ABE M & N values with 32K clock as source */
 204 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 205         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 206 };
 207
 208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 209 static const struct dpll_params
 210                 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
 211         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 212         {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 213         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
 214         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
 215         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 216         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 217         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 218 };
 219
 220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 221         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 222         {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
 223         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 224         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 225         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 226         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 227         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 228 };
 229
 230 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
 231         {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 232         {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 233         {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 234         {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 235         {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 236         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 237         {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 238 };
 239
 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 241         {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 242         {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 243         {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 244         {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 245         {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 246         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 247         {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 248 };
 249
 250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
 251         {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 12 MHz   */
 252         {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 20 MHz   */
 253         {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 254         {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 255         {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 26 MHz   */
 256         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 257         {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 258 };
 259
 260 struct dplls omap5_dplls_es1 = {
 261         .mpu = mpu_dpll_params_800mhz,
 262         .core = core_dpll_params_2128mhz_ddr532,
 263         .per = per_dpll_params_768mhz,
 264         .iva = iva_dpll_params_2330mhz,
 265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 266         .abe = abe_dpll_params_sysclk_196608khz,
 267 #else
 268         .abe = &abe_dpll_params_32k_196608khz,
 269 #endif
 270         .usb = usb_dpll_params_1920mhz,
 271         .ddr = NULL
 272 };
 273
 274 struct dplls omap5_dplls_es2 = {
 275         .mpu = mpu_dpll_params_1ghz,
 276         .core = core_dpll_params_2128mhz_ddr532_es2,
 277         .per = per_dpll_params_768mhz_es2,
 278         .iva = iva_dpll_params_2330mhz,
 279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 280         .abe = abe_dpll_params_sysclk_196608khz,
 281 #else
 282         .abe = &abe_dpll_params_32k_196608khz,
 283 #endif
 284         .usb = usb_dpll_params_1920mhz,
 285         .ddr = NULL
 286 };
 287
 288 struct dplls dra7xx_dplls = {
 289         .mpu = mpu_dpll_params_1ghz,
 290         .core = core_dpll_params_2128mhz_dra7xx,
 291         .per = per_dpll_params_768mhz_dra7xx,
 292         .abe = abe_dpll_params_sysclk2_361267khz,
 293         .iva = iva_dpll_params_2330mhz_dra7xx,
 294         .usb = usb_dpll_params_1920mhz,
 295         .ddr = ddr_dpll_params_2128mhz,
 296         .gmac = gmac_dpll_params_2000mhz,
 297 };
 298
 299 struct dplls dra72x_dplls = {
 300         .mpu = mpu_dpll_params_1ghz,
 301         .core = core_dpll_params_2128mhz_dra7xx,
 302         .per = per_dpll_params_768mhz_dra7xx,
 303         .abe = abe_dpll_params_sysclk2_361267khz,
 304         .iva = iva_dpll_params_2330mhz_dra7xx,
 305         .usb = usb_dpll_params_1920mhz,
 306         .ddr =  ddr_dpll_params_2664mhz,
 307         .gmac = gmac_dpll_params_2000mhz,
 308 };
 309
 310 struct pmic_data palmas = {
 311         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 312         .step = 10000, /* 10 mV represented in uV */
 313         /*
 314          * Offset codes 1-6 all give the base voltage in Palmas
 315          * Offset code 0 switches OFF the SMPS
 316          */
 317         .start_code = 6,
 318         .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
 319         .pmic_bus_init  = sri2c_init,
 320         .pmic_write     = omap_vc_bypass_send_value,
 321 };
 322
 323 /* The TPS659038 and TPS65917 are software-compatible, use common struct */
 324 struct pmic_data tps659038 = {
 325         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 326         .step = 10000, /* 10 mV represented in uV */
 327         /*
 328          * Offset codes 1-6 all give the base voltage in Palmas
 329          * Offset code 0 switches OFF the SMPS
 330          */
 331         .start_code = 6,
 332         .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
 333         .pmic_bus_init  = gpi2c_init,
 334         .pmic_write     = palmas_i2c_write_u8,
 335 };
 336
 337 struct vcores_data omap5430_volts = {
 338         .mpu.value = VDD_MPU,
 339         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 340         .mpu.pmic = &palmas,
 341
 342         .core.value = VDD_CORE,
 343         .core.addr = SMPS_REG_ADDR_8_CORE,
 344         .core.pmic = &palmas,
 345
 346         .mm.value = VDD_MM,
 347         .mm.addr = SMPS_REG_ADDR_45_IVA,
 348         .mm.pmic = &palmas,
 349 };
 350
 351 struct vcores_data omap5430_volts_es2 = {
 352         .mpu.value = VDD_MPU_ES2,
 353         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 354         .mpu.pmic = &palmas,
 355
 356         .core.value = VDD_CORE_ES2,
 357         .core.addr = SMPS_REG_ADDR_8_CORE,
 358         .core.pmic = &palmas,
 359
 360         .mm.value = VDD_MM_ES2,
 361         .mm.addr = SMPS_REG_ADDR_45_IVA,
 362         .mm.pmic = &palmas,
 363 };
 364
 365 struct vcores_data dra752_volts = {
 366         .mpu.value      = VDD_MPU_DRA752,
 367         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 368         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 369         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 370         .mpu.pmic       = &tps659038,
 371
 372         .eve.value      = VDD_EVE_DRA752,
 373         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 374         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 375         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 376         .eve.pmic       = &tps659038,
 377
 378         .gpu.value      = VDD_GPU_DRA752,
 379         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 380         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 381         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 382         .gpu.pmic       = &tps659038,
 383
 384         .core.value     = VDD_CORE_DRA752,
 385         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 386         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 387         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 388         .core.pmic      = &tps659038,
 389
 390         .iva.value      = VDD_IVA_DRA752,
 391         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 392         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 393         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 394         .iva.pmic       = &tps659038,
 395 };
 396
 397 struct vcores_data dra722_volts = {
 398         .mpu.value      = VDD_MPU_DRA72x,
 399         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 400         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 401         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 402         .mpu.pmic       = &tps659038,
 403
 404         .core.value     = VDD_CORE_DRA72x,
 405         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 406         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 407         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 408         .core.pmic      = &tps659038,
 409
 410         /*
 411          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 412          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 413          */
 414         .gpu.value      = VDD_GPU_DRA72x,
 415         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 416         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 417         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 418         .gpu.pmic       = &tps659038,
 419
 420         .eve.value      = VDD_EVE_DRA72x,
 421         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 422         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 423         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 424         .eve.pmic       = &tps659038,
 425
 426         .iva.value      = VDD_IVA_DRA72x,
 427         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 428         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 429         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 430         .iva.pmic       = &tps659038,
 431 };
 432
 433 /*
 434  * Enable essential clock domains, modules and
 435  * do some additional special settings needed
 436  */
 437 void enable_basic_clocks(void)
 438 {
 439         u32 const clk_domains_essential[] = {
 440                 (*prcm)->cm_l4per_clkstctrl,
 441                 (*prcm)->cm_l3init_clkstctrl,
 442                 (*prcm)->cm_memif_clkstctrl,
 443                 (*prcm)->cm_l4cfg_clkstctrl,
 444 #ifdef CONFIG_DRIVER_TI_CPSW
 445                 (*prcm)->cm_gmac_clkstctrl,
 446 #endif
 447                 0
 448         };
 449
 450         u32 const clk_modules_hw_auto_essential[] = {
 451                 (*prcm)->cm_l3_gpmc_clkctrl,
 452                 (*prcm)->cm_memif_emif_1_clkctrl,
 453                 (*prcm)->cm_memif_emif_2_clkctrl,
 454                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 455                 (*prcm)->cm_wkup_gpio1_clkctrl,
 456                 (*prcm)->cm_l4per_gpio2_clkctrl,
 457                 (*prcm)->cm_l4per_gpio3_clkctrl,
 458                 (*prcm)->cm_l4per_gpio4_clkctrl,
 459                 (*prcm)->cm_l4per_gpio5_clkctrl,
 460                 (*prcm)->cm_l4per_gpio6_clkctrl,
 461                 (*prcm)->cm_l4per_gpio7_clkctrl,
 462                 (*prcm)->cm_l4per_gpio8_clkctrl,
 463                 0
 464         };
 465
 466         u32 const clk_modules_explicit_en_essential[] = {
 467                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 468                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 469                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 470                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 471                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 472                 (*prcm)->cm_l4per_uart3_clkctrl,
 473                 (*prcm)->cm_l4per_i2c1_clkctrl,
 474 #ifdef CONFIG_DRIVER_TI_CPSW
 475                 (*prcm)->cm_gmac_gmac_clkctrl,
 476 #endif
 477
 478 #ifdef CONFIG_TI_QSPI
 479                 (*prcm)->cm_l4per_qspi_clkctrl,
 480 #endif
 481                 0
 482         };
 483
 484         /* Enable optional additional functional clock for GPIO4 */
 485         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 486                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 487
 488         /* Enable 96 MHz clock for MMC1 & MMC2 */
 489         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 490                         HSMMC_CLKCTRL_CLKSEL_MASK);
 491         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 492                         HSMMC_CLKCTRL_CLKSEL_MASK);
 493
 494         /* Set the correct clock dividers for mmc */
 495         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 496                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 497         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 498                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 499
 500         /* Select 32KHz clock as the source of GPTIMER1 */
 501         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 502                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 503
 504         do_enable_clocks(clk_domains_essential,
 505                          clk_modules_hw_auto_essential,
 506                          clk_modules_explicit_en_essential,
 507                          1);
 508
 509 #ifdef CONFIG_TI_QSPI
 510         setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
 511 #endif
 512
 513         /* Enable SCRM OPT clocks for PER and CORE dpll */
 514         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 515                         OPTFCLKEN_SCRM_PER_MASK);
 516         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 517                         OPTFCLKEN_SCRM_CORE_MASK);
 518 }
 519
 520 void enable_basic_uboot_clocks(void)
 521 {
 522         u32 const clk_domains_essential[] = {
 523 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 524                 (*prcm)->cm_ipu_clkstctrl,
 525 #endif
 526                 0
 527         };
 528
 529         u32 const clk_modules_hw_auto_essential[] = {
 530                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 531                 0
 532         };
 533
 534         u32 const clk_modules_explicit_en_essential[] = {
 535                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 536                 (*prcm)->cm_l4per_i2c2_clkctrl,
 537                 (*prcm)->cm_l4per_i2c3_clkctrl,
 538                 (*prcm)->cm_l4per_i2c4_clkctrl,
 539 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 540                 (*prcm)->cm_ipu_i2c5_clkctrl,
 541 #else
 542                 (*prcm)->cm_l4per_i2c5_clkctrl,
 543 #endif
 544                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 545                 (*prcm)->cm_l3init_fsusb_clkctrl,
 546                 0
 547         };
 548         do_enable_clocks(clk_domains_essential,
 549                          clk_modules_hw_auto_essential,
 550                          clk_modules_explicit_en_essential,
 551                          1);
 552 }
 553
 554 #ifdef CONFIG_TI_EDMA3
 555 void enable_edma3_clocks(void)
 556 {
 557         u32 const clk_domains_edma3[] = {
 558                 0
 559         };
 560
 561         u32 const clk_modules_hw_auto_edma3[] = {
 562                 (*prcm)->cm_l3main1_tptc1_clkctrl,
 563                 (*prcm)->cm_l3main1_tptc2_clkctrl,
 564                 0
 565         };
 566
 567         u32 const clk_modules_explicit_en_edma3[] = {
 568                 0
 569         };
 570
 571         do_enable_clocks(clk_domains_edma3,
 572                          clk_modules_hw_auto_edma3,
 573                          clk_modules_explicit_en_edma3,
 574                          1);
 575 }
 576
 577 void disable_edma3_clocks(void)
 578 {
 579         u32 const clk_domains_edma3[] = {
 580                 0
 581         };
 582
 583         u32 const clk_modules_disable_edma3[] = {
 584                 (*prcm)->cm_l3main1_tptc1_clkctrl,
 585                 (*prcm)->cm_l3main1_tptc2_clkctrl,
 586                 0
 587         };
 588
 589         do_disable_clocks(clk_domains_edma3,
 590                           clk_modules_disable_edma3,
 591                           1);
 592 }
 593 #endif
 594
 595 #ifdef CONFIG_USB_DWC3
 596 void enable_usb_clocks(int index)
 597 {
 598         u32 cm_l3init_usb_otg_ss_clkctrl = 0;
 599
 600         if (index == 0) {
 601                 cm_l3init_usb_otg_ss_clkctrl =
 602                         (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
 603                 /* Enable 960 MHz clock for dwc3 */
 604                 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 605                              OPTFCLKEN_REFCLK960M);
 606
 607                 /* Enable 32 KHz clock for dwc3 */
 608                 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 609                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 610         } else if (index == 1) {
 611                 cm_l3init_usb_otg_ss_clkctrl =
 612                         (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
 613                 /* Enable 960 MHz clock for dwc3 */
 614                 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
 615                              OPTFCLKEN_REFCLK960M);
 616
 617                 /* Enable 32 KHz clock for dwc3 */
 618                 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
 619                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 620
 621                 /* Enable 60 MHz clock for USB2PHY2 */
 622                 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
 623                              L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
 624         }
 625
 626         u32 const clk_domains_usb[] = {
 627                 0
 628         };
 629
 630         u32 const clk_modules_hw_auto_usb[] = {
 631                 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
 632                 cm_l3init_usb_otg_ss_clkctrl,
 633                 0
 634         };
 635
 636         u32 const clk_modules_explicit_en_usb[] = {
 637                 0
 638         };
 639
 640         do_enable_clocks(clk_domains_usb,
 641                          clk_modules_hw_auto_usb,
 642                          clk_modules_explicit_en_usb,
 643                          1);
 644 }
 645
 646 void disable_usb_clocks(int index)
 647 {
 648         u32 cm_l3init_usb_otg_ss_clkctrl = 0;
 649
 650         if (index == 0) {
 651                 cm_l3init_usb_otg_ss_clkctrl =
 652                         (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
 653                 /* Disable 960 MHz clock for dwc3 */
 654                 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 655                              OPTFCLKEN_REFCLK960M);
 656
 657                 /* Disable 32 KHz clock for dwc3 */
 658                 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 659                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 660         } else if (index == 1) {
 661                 cm_l3init_usb_otg_ss_clkctrl =
 662                         (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
 663                 /* Disable 960 MHz clock for dwc3 */
 664                 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
 665                              OPTFCLKEN_REFCLK960M);
 666
 667                 /* Disable 32 KHz clock for dwc3 */
 668                 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
 669                              USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 670
 671                 /* Disable 60 MHz clock for USB2PHY2 */
 672                 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
 673                              L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
 674         }
 675
 676         u32 const clk_domains_usb[] = {
 677                 0
 678         };
 679
 680         u32 const clk_modules_disable[] = {
 681                 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
 682                 cm_l3init_usb_otg_ss_clkctrl,
 683                 0
 684         };
 685
 686         do_disable_clocks(clk_domains_usb,
 687                           clk_modules_disable,
 688                           1);
 689 }
 690 #endif
 691
 692 const struct ctrl_ioregs ioregs_omap5430 = {
 693         .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 694         .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
 695         .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
 696         .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
 697         .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
 698 };
 699
 700 const struct ctrl_ioregs ioregs_omap5432_es1 = {
 701         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 702         .ctrl_lpddr2ch = 0x0,
 703         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
 704         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 705         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 706         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 707         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 708         .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 709 };
 710
 711 const struct ctrl_ioregs ioregs_omap5432_es2 = {
 712         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 713         .ctrl_lpddr2ch = 0x0,
 714         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 715         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
 716         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 717         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 718         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 719         .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 720 };
 721
 722 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 723         .ctrl_ddrch = 0x40404040,
 724         .ctrl_lpddr2ch = 0x40404040,
 725         .ctrl_ddr3ch = 0x80808080,
 726         .ctrl_ddrio_0 = 0x00094A40,
 727         .ctrl_ddrio_1 = 0x04A52000,
 728         .ctrl_ddrio_2 = 0x84210000,
 729         .ctrl_emif_sdram_config_ext = 0x0001C1A7,
 730         .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 731         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 732 };
 733
 734 const struct ctrl_ioregs ioregs_dra72x_es1 = {
 735         .ctrl_ddrch = 0x40404040,
 736         .ctrl_lpddr2ch = 0x40404040,
 737         .ctrl_ddr3ch = 0x60606080,
 738         .ctrl_ddrio_0 = 0x00094A40,
 739         .ctrl_ddrio_1 = 0x04A52000,
 740         .ctrl_ddrio_2 = 0x84210000,
 741         .ctrl_emif_sdram_config_ext = 0x0001C1A7,
 742         .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 743         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 744 };
 745
 746 void __weak hw_data_init(void)
 747 {
 748         u32 omap_rev = omap_revision();
 749
 750         switch (omap_rev) {
 751
 752         case OMAP5430_ES1_0:
 753         case OMAP5432_ES1_0:
 754         *prcm = &omap5_es1_prcm;
 755         *dplls_data = &omap5_dplls_es1;
 756         *omap_vcores = &omap5430_volts;
 757         *ctrl = &omap5_ctrl;
 758         break;
 759
 760         case OMAP5430_ES2_0:
 761         case OMAP5432_ES2_0:
 762         *prcm = &omap5_es2_prcm;
 763         *dplls_data = &omap5_dplls_es2;
 764         *omap_vcores = &omap5430_volts_es2;
 765         *ctrl = &omap5_ctrl;
 766         break;
 767
 768         case DRA752_ES1_0:
 769         case DRA752_ES1_1:
 770         case DRA752_ES2_0:
 771         *prcm = &dra7xx_prcm;
 772         *dplls_data = &dra7xx_dplls;
 773         *omap_vcores = &dra752_volts;
 774         *ctrl = &dra7xx_ctrl;
 775         break;
 776
 777         case DRA722_ES1_0:
 778         *prcm = &dra7xx_prcm;
 779         *dplls_data = &dra72x_dplls;
 780         *omap_vcores = &dra722_volts;
 781         *ctrl = &dra7xx_ctrl;
 782         break;
 783
 784         default:
 785                 printf("\n INVALID OMAP REVISION ");
 786         }
 787 }
 788
 789 void get_ioregs(const struct ctrl_ioregs **regs)
 790 {
 791         u32 omap_rev = omap_revision();
 792
 793         switch (omap_rev) {
 794         case OMAP5430_ES1_0:
 795         case OMAP5430_ES2_0:
 796                 *regs = &ioregs_omap5430;
 797                 break;
 798         case OMAP5432_ES1_0:
 799                 *regs = &ioregs_omap5432_es1;
 800                 break;
 801         case OMAP5432_ES2_0:
 802                 *regs = &ioregs_omap5432_es2;
 803                 break;
 804         case DRA752_ES1_0:
 805         case DRA752_ES1_1:
 806         case DRA752_ES2_0:
 807                 *regs = &ioregs_dra7xx_es1;
 808                 break;
 809         case DRA722_ES1_0:
 810                 *regs = &ioregs_dra72x_es1;
 811                 break;
 812
 813         default:
 814                 printf("\n INVALID OMAP REVISION ");
 815         }
 816 }